参数资料
型号: MPC8358EVRAGDDA
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 400 MHz, RISC PROCESSOR, PBGA668
封装: 29 X 29 MM, 1.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-668
文件页数: 32/95页
文件大小: 1225K
代理商: MPC8358EVRAGDDA
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
38
Freescale Semiconductor
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
Figure 20 shows the MII management AC timing diagram.
Figure 20. MII Management Interface Timing Diagram
8.3.3
IEEE 1588 Timer AC Specifications
Table 37 provides the IEEE 1588 timer AC specifications.
MDC fall time
tMDHF
10
ns
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management
data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
Also, tMDRDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state
(V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is 8.3 MHz
and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz and the minimum
frequency is 1.7 MHz).
3. This parameter is dependent on the ce_clk speed (that is, for a ce_clk of 200 MHz, the delay is 90 ns and for a ce_clk of
300 MHz, the delay is 63 ns).
Table 37. IEEE 1588 Timer AC Specifications
Parameter
Symbol
Min
Max
Unit
Notes
Timer clock frequency
tTMRCK
070
MHz
1
Input setup to timer clock
tTMRCKS
———
2, 3
Input hold from timer clock
tTMRCKH
———
2, 3
Output clock to output valid
tGCLKNV
06
ns
Table 36. MII Management AC Timing Specifications (continued)
At recommended operating conditions with LVDD is 3.3 V ± 10%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
Notes
MDC
tMDRDXKH
tMDC
tMDCH
tMDCR
tMDHF
tMDTKHDX
MDIO
(Input)
(Output)
tMDRDVKH
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