参数资料
型号: MPC8378ECVRALFA
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 333 MHz, MICROPROCESSOR, PBGA689
封装: 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件页数: 35/125页
文件大小: 894K
代理商: MPC8378ECVRALFA
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
17
6
DDR1 and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8378E. Note that
DDR1 SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V.
6.1
DDR1 and DDR2 SDRAM DC Electrical Characteristics
The following table provides the recommended operating conditions for the DDR2 SDRAM component(s) of the device when
GVDD(typ) = 1.8 V.
Table 14 provides the DDR2 capacitance when GVDD(typ) = 1.8 V.
This table provides the recommended operating conditions for the DDR SDRAM component(s) when GVDD(typ) = 2.5 V.
Table 13. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter
Symbol
Min
Max
Unit
Note
I/O supply voltage
GVDD
1.71
1.89
V
I/O reference voltage
MVREF
0.49
GV
DD
0.51
GV
DD
V
2, 5
I/O termination voltage
VTT
MVREF –0.04
MVREF +0.04
V
Input high voltage
VIH
MVREF + 0.140
GVDD +0.3
V
Input low voltage
VIL
–0.3
MVREF –0.140
V
Output leakage current
IOZ
–50
50
A
Output high current (VOUT =1.40V)
IOH
–13.4
mA
Output low current (VOUT =0.3 V)
IOL
13.4
mA
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V
V
OUT GVDD.
5. See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.
Table 14. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V
Parameter
Symbol
Min
Max
Unit
Note
Input/output capacitance: DQ, DQS, DQS
CIO
68
pF
Delta input/output capacitance: DQ, DQS, DQS
CDIO
—0.5
pF
Note:
1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA =25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
Table 15. DDR SDRAM DC Electrical Characteristics for GVDD (typ) = 2.5 V
Parameter
Symbol
Min
Max
Unit
Note
I/O supply voltage
GVDD
2.375
2.625
V
I/O reference voltage
MVREF
0.49
GV
DD
0.51
GV
DD
V
I/O termination voltage
VTT
MVREF – 0.04
MVREF + 0.04
V
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