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参数资料
| 型号： | MPC850ZT33 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | RISC PROCESSOR, PBGA256 |
| 封装： | PLASTIC, BGA-256 |
| 文件页数： | 11/12页 |
| 文件大小： | 70K |
| 代理商： | MPC850ZT33 |
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MPC850/MPC850SE Technical Summary
MOTOROLA
1.2 Architecture Overview
The MPC850 integrates a high-performance embedded PowerPC core with high-performance, low-power
peripherals and extends the Motorola family of microprocessors into cost-sensitive, high-volume
communications and networking products.
The MPC850 adopts a dual-processor architecture providing a high-performance, general-purpose RISC
integer processor, an embedded PowerPC core for application programming use, and a special-purpose
32-bit scalar RISC communication processor module. The MPC850 block diagram is shown in Figure 1.
1.2.1 Embedded PowerPC Core
The PowerPC core is compliant with the PowerPC architecture definition. It has a fully-static design that
consists of three functional blocks—integer block, hardware multiplier/divider, and load/store block. It
executes all integer and load/store operations directly on the hardware. The core supports integer operations
on a 32-bit internal data path and 32-bit arithmetic hardware. Its interface to the internal and external buses
is 32 bits. The core uses a two-instruction load/store queue, four-instruction prefetch queue, and a
six-instruction history buffer. The core performs branch folding and branch prediction with conditional
prefetch, but without conditional execution. The core can operate on 32-bit external operands with one bus
cycle. The PowerPC integer block supports 32- x 32-bit fixed-point general-purpose registers. It can execute
one integer instruction on each clock cycle. Each element in the integer block is only clocked when valid
data is present in the data queue ready for operation, which reduces the amount of power consumed to the
amount needed to perform an operation.
The PowerPC processor is integrated with the memory management units and 2-Kbyte instruction and
1-Kbyte data caches. The memory management units (MMUs) provide an 8-entry, fully-associative
instruction and data TLB, with multiple page sizes of 4 Kbytes (1-Kbyte protection), 16 Kbytes, 512 Kbytes,
and 8 Mbytes. It supports 16 virtual address spaces with eight protection groups. Three special registers are
available as scratch registers to support software tablewalk and update.
The instruction cache is 2 Kbytes, two-way, set associative with physical addressing. It allows single-cycle
access on hit with no added latency for miss. It has four words per line and supports burst linefill using an
LRU replacement algorithm. The cache can be locked on a line by line basis for application critical routines.
The data cache is 1 Kbyte, two-way, set associative with physical addressing. It allows single-cycle access
on hit with one added clock latency for miss. It has four words per line and supports burst linefill using an
LRU replacement algorithm. The cache can be locked on a line by line basis for application critical routines
and can be programmed to support copy-back or write-through via the memory management unit. The
inhibit mode can be programmed per MMU page.
The PowerPC processor with its instruction and data caches can deliver approximately 87 MIPS at 66MHz
(using Dhrystone 2.1) or 115 K Dhrystones, based on the assumption that it is issuing one instruction per
cycle with a cache hit rate of 94%.
1.2.2 Communication Processor Module
The communication processor module (CPM) has features that allow the MPC850 to excel in
communications and networking products. These features are divided into two blocks:
Communication processor
Fourteen serial DMA channels and two independent DMA channels
The communication processor module provides the communication features of the MPC850. It includes a
RISC processor with multiply accumulate (MAC) hardware, two serial communication controllers (SCCs),
two serial management controllers (SMCs), one dedicated serial channel for the universal serial bus (USB),
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