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参数资料
| 型号： | MPC850ZT33 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | RISC PROCESSOR, PBGA256 |
| 封装： | PLASTIC, BGA-256 |
| 文件页数： | 12/12页 |
| 文件大小： | 70K |
| 代理商： | MPC850ZT33 |
MOTOROLA
MPC850/MPC850SE Technical Summary
9
one interprocessor-integrated circuit (I2C) port, one serial peripheral interface (SPI), 8-Kbyte dual-port
RAM, an interrupt controller, a time-slot assigner, and four independent baud rate generators.
Fourteen serial DMA channels on the MPC850 support the SCCs, SMCs, USB channel, SPI, and I2C. The
IDMAs provide two channels of general-purpose DMA capability for each communication channel. They
offer high-speed transfers, 32-bit memory to memory data transfers, buffer chaining, and independent
request and acknowledge logic. The RISC controller can access the IDMA registers directly in the buffer
chaining modes.
1.2.3 System Interface Unit
Although the PowerPC core is always a 32-bit device internally, it can be configured to operate with an 8-,
16- or 32-bit data bus. Regardless of the choice of the system bus size, dynamic bus sizing is supported,
which allows 8-, 16-, and 32-bit peripherals and memory to coexist on the 32-bit system bus. The system
interface unit supports traditional 68000 big-endian memory systems, traditional x86 little-endian memory
systems, and PowerPC little-endian memory systems. It also provides power management functions, reset
control, a PowerPC decrementer, PowerPC time base, and real-time clock.
The memory controller supports up to eight memory banks with glueless interfaces to DRAM, SRAM,
PSRAM, EPROM, Flash EPROM, SDRAM, EDO and other peripherals with two-clock initial access to
external SRAM and bursting support. It provides variable block sizes from 32 Kbytes to 256 Mbytes. The
memory controller provides 0 to 15 wait states for each bank of memory and can use address type matching
to qualify each memory bank access. It provides four byte-enable signals for varying width devices, one
output enable signal, and one boot chip-select available at reset.
The DRAM interface supports 8-, 16-, and 32-bit ports. It uses a programmable state machine to support
almost any memory interface. Memory banks can be defined in depths of 256 Kbytes, 512 Kbytes, 1 Mbyte,
2 Mbytes, 4 Mbytes, 8 Mbytes, 16 Mbytes, 32 Mbytes, or 64 Mbytes for all port sizes. In addition, the
memory depth can be defined as 64 Kbytes and 128 Kbytes for 8-bit memory or 128 Mbytes and
256 Mbytes for 32-bit memory. The DRAM controller supports page mode access for successive transfers
within bursts. The MPC850 supports a glueless interface to one bank of DRAM, while external buffers are
required for additional memory banks. The refresh unit provides CAS before RAS, a programmable refresh
timer, refresh active during external reset, disable refresh modes, and stacking for a maximum of seven
refresh cycles.
The PCMCIA-ATA interface is a master controller that is compliant with release 2.1. The interface supports
one independent PCMCIA socket with external transceivers or buffers required. It provides eight memory
or I/O windows that can be allocated to the socket. If the PCMCIA port is not being used as a card interface,
it can be used as a general-purpose input with interrupt capability.
1.3 Power Management
The MPC850 supports a wide range of power management features including full-high, full-low, doze,
sleep, deep-sleep, and low-power stop. In full-high mode, the MPC850 is fully powered with all internal
units operating at the full speed of the processor. Full-low mode is the same as full-high, but operates at a
lower frequency. There is a gear mode determined by a clock divider that allows the operating system to
reduce the operational frequency of the processor.
Doze mode disables core functional units except the time base, decrementer, PLL, memory controller,
real-time clock, and places the communication processor module in low-power standby mode. Sleep mode
is the next lower power mode that disables everything except the real-time clock and periodic interrupt
timer, thus leaving the PLL active for quick wake-up. The deep-sleep mode then disables the PLL for lower
power, but slower wake-up. Low-power stop disables all logic in the processor except the minimum logic
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