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| 型号： | MPC852TVR50A |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 14/80页 |
| 文件大小： | 0K |
| 描述： | IC MPU POWERQUICC 50MHZ 256PBGA |
| 标准包装： | 60 |
| 系列： | MPC8xx |
| 处理器类型： | 32-位 MPC8xx PowerQUICC |
| 速度： | 50MHz |
| 电压： | 1.8V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BGA |
| 供应商设备封装： | 256-PBGA（23x23） |
| 包装： | 托盘 |
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MPC852T PowerQUICC Hardware Specifications, Rev. 4
Freescale Semiconductor
21
Bus Signal Timing
B35b
A(0:31), BADDR(28:30), and D(0:31) to
BS valid - as requested by control bit BST2
in the corresponding word in the UPM
(MIN = 0.75
× B1 – 2.00)
20.70
—
16.70
—
13.00
—
9.40
—
ns
B36
A(0:31), BADDR(28:30), and D(0:31) to
GPL valid as requested by control bit GxT4
in the corresponding word in the UPM
(MIN = 0.25
× B1 – 2.00)
5.60
—
4.30
—
3.00
—
1.80
—
ns
B37
UPWAIT valid to CLKOUT falling edge10
(MIN = 0.00
× B1 + 6.00)
6.00
—
6.00
—
6.00
—
6.00
—
ns
B38
CLKOUT falling edge to UPWAIT valid10
(MIN = 0.00
× B1 + 1.00)
1.00
—
1.00
—
1.00
—
1.00
—
ns
B39
AS valid to CLKOUT rising edge11
(MIN = 0.00
× B1 + 7.00)
7.00
—
7.00
—
7.00
—
7.00
—
ns
B40
A(0:31), TSIZ(0:1), RD/WR, BURST, valid
to CLKOUT rising edge
(MIN = 0.00
× B1 + 7.00)
7.00
—
7.00
—
7.00
—
7.00
—
ns
B41
TS valid to CLKOUT rising edge (setup
time) (MIN = 0.00
× B1 + 7.00)
7.00
—
7.00
—
7.00
—
7.00
—
ns
B42
CLKOUT rising edge to TS valid (hold
time) (MIN = 0.00
× B1 + 2.00)
2.00
—
2.00
—
2.00
—
2.00
—
ns
B43
AS negation to memory controller signals
negation (MAX = TBD)
—TBD
ns
1 If the rate of change of the frequency of EXTAL is slow (that is, it does not jump between the minimum and maximum values
in one cycle) or the frequency of the jitter is fast (that is, it does not stay at an extreme value for a long time), then the maximum
allowed jitter on EXTAL can be up to 2%.
2 For part speeds above 50MHz, use 9.80ns for B11a.
3 The timing required for BR input is relevant when the MPC852T is selected to work with internal bus arbiter. The timing for BG
input is relevant when the MPC852T is selected to work with external bus arbiter.
4 For part speeds above 50MHz, use 2ns for B17.
5 The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is
asserted.
6 For part speeds above 50MHz, use 2ns for B19.
7 The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for read
accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats where DLT3 = 1 in the
UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
8 This formula applies to bus operation up to 50 MHz.
9 The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
10 The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in B37 and
B38 are specified to enable the freeze of the UPM output signals as described in Figure 19.
11 The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior specified
in Figure 22.
Table 9. Bus Operation Timings (continued)
Num
Characteristic
33 MHz
40 MHz
50 MHz
66 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
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