参数资料
型号: MPC852TVR80
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 80 MHz, RISC PROCESSOR, PBGA256
封装: PLASTIC, BGA-256
文件页数: 12/72页
文件大小: 1210K
代理商: MPC852TVR80
2
MPC852T Hardware Specifications
MOTOROLA
Features
applications. It particularly excels in Ethernet control applications, including CPE equipment, Ethernet
routers and hubs, VoIP clients, and WiFi access points.
The MPC852T is a PowerPC architecture-based derivative of the Motorola MPC860 Quad Integrated
Communications Controller (PowerQUICC). The CPU on the MPC852T is the MPC8xx core, a 32-bit
microprocessor that implements the PowerPC architecture, incorporating memory management units
(MMUs) and instruction and data caches. The MPC852T is the subset of this family of devices.
2Features
The MPC852T is comprised of three modules that each use the 32-bit internal bus: the MPC8xx core, the
system integration unit (SIU), and the communication processor module (CPM). Figure 1 shows the
MPC852T block diagram.
The following list summarizes the key MPC852T features:
Embedded MPC8xx core up to 100 MHz
Maximum frequency operation of the external bus is 66 MHz
— The 50 MHz / 66 MHz core frequencies support both 1:1 and 2:1 modes.
— The 80 MHz / 100 MHz core frequencies support 2:1 mode only.
Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with 32 32-bit
general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution.
— 4-Kbyte data cache and 4-Kbyte instruction cache
– 4-Kbyte instruction cache is two-way, set-associative with 128 sets.
– 4-Kbyte data cache is two-way, set-associative with 128 sets.
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
cache blocks.
– Caches are physically addressed, implement a least recently used (LRU) replacement
algorithm, and are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully associative instruction, and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
spaces, and 16 protection groups
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank
— Up to 30 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory
devices
— DRAM controller-programmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, and one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbytes–256 Mbytes)
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