参数资料
型号: MPC852TVR80
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 80 MHz, RISC PROCESSOR, PBGA256
封装: PLASTIC, BGA-256
文件页数: 3/72页
文件大小: 1210K
代理商: MPC852TVR80
MOTOROLA
MPC852T Hardware Specifications
11
Power Supply and Power Sequencing
9
Power Supply and Power Sequencing
This section provides design considerations for the MPC852T power supply. The MPC852T has a core
voltage (VDDL) and PLL voltage (VDDSYN) that operates at a lower voltage than the I/O voltage VDDH. The
I/O section of the MPC852T is supplied with 3.3 V across VDDH and VSS (GND).
The signal PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15] PD[3:15], TDI,
TDO, TCK, TRST, TMS, MII_TXEN, MII_MDIO are 5 V-tolerant. All inputs cannot be more than 2.5 V
greater than VDDH. In addition, 5 V-tolerant pins can not exceed 5.5 V, and remaining input pins cannot
exceed 3.465 V. This restriction applies to power-on reset or power down and normal operation.
One consequence of multiple power supplies is that when power is initially applied, the voltage rails ramp
up at different rates. The rates depend on the nature of the power supply, the type of load on each power
supply, and the manner in which different voltages are derived. The following restrictions apply:
VDDL must not exceed VDDH during power-on reset or power down.
VDDL must not exceed 1.9 V, and VDDH must not exceed 3.465.
These cautions are necessary for the long-term reliability of the part. If they are violated, the electrostatic
discharge (ESD) protection diodes are forward-biased, and excessive current can flow through these diodes.
If the system power supply design does not control the voltage sequencing, the circuit shown in Figure 2
can be added to meet these requirements. The MUR420 Schottky diodes control the maximum potential
difference between the external bus and core power supplies on power-on reset, and the 1N5820 diodes
regulate the maximum potential difference on power-down.
Figure 2. Example Voltage Sequencing Circuit
10 Mandatory Reset Configurations
The MPC852T requires a mandatory configuration during reset.
If hardware reset configuration word (HRCW) is enabled, by asserting the RSTCONF during HRESET
assertion, the HRCW[DBGC] value that is needed to be set to binary X1 in the hardware reset configuration
word (HRCW) and the SIUMCR[DBGC] should be programmed with the same value in the boot code after
reset.
If hardware reset configuration word (HRCW) is disabled, by negating the RSTCONF during the HRESET
assertion, the SIUMCR[DBGC] should be programmed with binary X1 in the boot code after reset.
The MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR, PCPAR, and PCDIR should be configured
with the mandatory value in Table 6 in the boot code after the reset deasserts.
VDDH
VDDL
1N5820
MUR420
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MPC852TZT100A 功能描述:微处理器 - MPU POWER QUICC II HIP6W RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC852TZT50A 功能描述:微处理器 - MPU POWER QUICC II HIP6W RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC852TZT66A 功能描述:微处理器 - MPU POWER QUICC II HIP6W RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
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