参数资料
型号: MPC8535EBVTATHA
厂商: Freescale Semiconductor
文件页数: 78/126页
文件大小: 0K
描述: MCU PWRQUICC II 1250MHZ 783-PBGA
标准包装: 1
系列: MPC85xx
处理器类型: 32-位 MPC85xx PowerQUICC III
速度: 1.25GHz
电压: 1V
安装类型: 表面贴装
封装/外壳: 783-BBGA,FCBGA
供应商设备封装: 783-FCPBGA(29x29)
包装: 托盘
其它名称: MPC8535EBVTATH
MPC8535EBVTATH-ND
Electrical Characteristics
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
55
2.9.3.3
SGMII Transmitter and Receiver DC Electrical Characteristics
The following tables describe the SGMII SerDes transmitter and receiver AC-Coupled DC electrical characteristics.
Transmitter DC characteristics are measured at the transmitter outputs (SD2_TX[n] and SD2_TX[n]) as depicted in Figure 30.
Table 39. SGMII DC Transmitter Electrical Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Supply Voltage
X2VDD
0.95
1.0
1.05
V
Output high voltage
VOH
X2VDD-Typ/2 +
|VOD|-max/2
mV
1
Output low voltage
VOL
X2VDD-Typ/2 -
|VOD|-max/2
——
mV
1
Output ringing
VRING
——
10
%
Output differential voltage2, 3, 5
|VOD|
323
500
725
mV
Equalization
setting: 1.0x
296
459
665
Equalization
setting: 1.09x
269
417
604
Equalization
setting: 1.2x
243
376
545
Equalization
setting: 1.33x
215
333
483
Equalization
setting: 1.5x
189
292
424
Equalization
setting: 1.71x
162
250
362
Equalization
setting: 2.0x
Output offset voltage
VOS
425
500
575
mV
1, 4
Output impedance (single-ended)
RO
40
60
Ω
Mismatch in a pair
RO
——
10
%
Change in VOD between “0” and “1”
|VOD|—
25
mV
Change in VOS between “0” and “1”
VOS
——
25
mV
Output current on short to GND
ISA, ISB
——
40
mA
Notes:
1. This will not align to DC-coupled SGMII. X2VDD-Typ=1.0V.
2. |VOD| = |VSD2_TXn - VSD2_TXn|. |VOD| is also referred as output differential peak voltage. VTX-DIFFp-p = 2*|VOD|.
3. The |VOD| value shown in the table assumes the following transmit equalization setting in the XMITEQAB (for SerDes 2 lanes
A & B) or XMITEQEF (for SerDes 2 lanes E & E) bit field of the chip’s SerDes 2 control register:
The MSbit (bit 0) of the above bit field is set to zero (selecting the full VDD-DIFF-p-p amplitude - power up default);
The LSbits (bit [1:3]) of the above bit field is set based on the equalization setting shown in table.
4. VOS is also referred to as output common mode voltage.
5.The |VOD| value shown in the Typ column is based on the condition of X2VDD-Typ=1.0V, no common mode offset variation
(VOS =550mV), SerDes2 transmitter is terminated with 100-
Ω differential load between SD2_TX[n] and SD2_TX[n].
Δ
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