参数资料
型号: MPC8536EAVTAVLA
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA783
封装: 29 X 29 MM, 2.80 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-783
文件页数: 121/127页
文件大小: 1893K
代理商: MPC8536EAVTAVLA
High-Speed Serial Interfaces
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
93
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. See the Differential Mode and
Single-ended Mode description below for further detailed requirements.
The maximum average current requirement that also determines the common mode voltage range
— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the
maximum average current allowed for each input pin is 8mA. In this case, the exact common mode input voltage
is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the
following bullet for more detail), since the input is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V/50 = 8 mA)
while the minimum common mode input level is 0.1V above SnGND (xcorevss). For example, a clock with a
50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0mA to 16mA
(0–0.8 V), such that each phase of the differential input has a single-ended swing from 0 V to 800mV with the
common mode voltage at 400mV.
— If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50
Ω to SnGND (xcorevss)
DC, or it exceeds the maximum input current limitations, then it must be AC-coupled off-chip.
The input amplitude requirement
— This requirement is described in detail in the following sections.
Figure 58. Receiver of SerDes Reference Clocks
Input
Amp
50
Ω
50
Ω
SDn_REF_CLK
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