参数资料
型号: MPC8536EAVTAVLA
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA783
封装: 29 X 29 MM, 2.80 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-783
文件页数: 56/127页
文件大小: 1893K
代理商: MPC8536EAVTAVLA
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
DDR2 and DDR3 SDRAM
Freescale Semiconductor
34
3
Figure 8 shows the DDR2 and DDR3 SDRAM interface input timing diagram.
Figure 8. DDR SDRAM Input Timing Diagram
Table 17. DDR3 SDRAM Input AC Timing Specifications for 1.5-V Interface
At recommended operating conditions with GVDD of 1.5 V ± 5%. DDR3 data rate is between 606MHz and 667MHz.
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
VIL
—MVREF – 0.175
V
AC input high voltage
VIH
MVREF + 0.175
V
Table 18. DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications
At recommended operating conditions with GVDD of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3.
Parameter
Symbol
Min
Max
Unit
Notes
Controller Skew for MDQS—MDQ/MECC
tCISKEW
ps
1, 2
667 MHz
–240
240
3
533 MHz
–300
300
400 MHz
–365
365
Note:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that will
be captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be determined
by the following equation: tDISKEW =+/-(T/4 - abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute value
of tCISKEW.
3. Maximum DDR2 and DDR3 frequency is 667MHz.
MCK[n]
tMCK
MDQ[x]
MDQS[n]
tDISKEW
D1
D0
tDISKEW
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