参数资料
型号: MPC8536EBVTAVLA
厂商: Freescale Semiconductor
文件页数: 77/126页
文件大小: 0K
描述: MPU PWRQUICC III 1500MHZ 783PBGA
产品培训模块: MPC8536E QUICC III Processor
标准包装: 1
系列: MPC85xx
处理器类型: 32-位 MPC85xx PowerQUICC III
速度: 1.5GHz
电压: 1.1V
安装类型: 表面贴装
封装/外壳: 783-BBGA,FCBGA
供应商设备封装: 783-FCPBGA(29x29)
包装: 托盘
其它名称: MPC8536EBVTAVL
MPC8536EBVTAVL-ND
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Electrical Characteristics
Freescale Semiconductor
54
This figure provides the AC test load for eTSEC.
Figure 27. eTSEC AC Test Load
This figure shows the RMII receive AC timing diagram.
Figure 28. RMII Receive AC Timing Diagram
2.9.3
SGMII Interface Electrical Characteristics
Each SGMII port features a 4-wire AC-Coupled serial link from the dedicated SerDes 2 interface of the chip as shown in
Figure 29, where CTX is the external (on board) AC-Coupled capacitor. Each output pin of the SerDes transmitter differential
pair features 50-
Ω output impedance. Each input of the SerDes receiver differential pair features 50-Ω on-die termination to
S2GND (xcorevss). The reference circuit of the SerDes transmitter and receiver is shown in Figure 68.
When an eTSEC port is configured to operate in SGMII mode, the parallel interface’s output signals of this eTSEC port can be
left floating. The input signals should be terminated based on the guidelines described in Section 3.6, “Connection
Recommendations,as long as such termination does not violate the desired POR configuration requirement on these pins, if
applicable.
Fall time TSECn_RX_CLK (80%–20%)
tRMRF
1.0
2.0
ns
RXD[1:0], CRS_DV, RX_ER setup time to TSECn_RX_CLK rising edge
tRMRDV
4.0
——ns
RXD[1:0], CRS_DV, RX_ER hold time to TSECn_RX_CLK rising edge
tRMRDX
2.0
——ns
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going
to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals
(D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For example, the
subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall).
Table 37. RMII Receive AC Timing Specifications (continued)
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Output
Z0 = 50 Ω
LVDD/2
RL = 50 Ω
TSECn_RX_CLK
RXD[1:0]
tRMRDX
tRMR
tRMRH
tRMRR
tRMRF
CRS_DV
RX_ER
tRMRDV
Valid Data
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