参数资料
型号: MPC8555CPXAKDX
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 600 MHz, RISC PROCESSOR, PBGA783
封装: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件页数: 45/88页
文件大小: 1244K
代理商: MPC8555CPXAKDX
MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
5
Overview
— Can be partitioned into 128-Kbyte L2 cache plus 128-Kbyte SRAM
— Full ECC support on 64-bit boundary in both cache and SRAM modes
— SRAM operation supports relocation and is byte-accessible
— Cache mode supports instruction caching, data caching, or both
— External masters can force data to be allocated into the cache through programmed memory
ranges or special transaction types (stashing)
— Eight-way set-associative cache organization (1024 sets of 32-byte cache lines)
— Supports locking the entire cache or selected lines
– Individual line locks set and cleared through Book E instructions or by externally mastered
transactions
— Global locking and flash clearing done through writes to L2 configuration registers
— Instruction and data locks can be flash cleared separately
— Read and write buffering for internal bus accesses
Address translation and mapping unit (ATMU)
— Eight local access windows define mapping within local 32-bit address space
— Inbound and outbound ATMUs map to larger external address spaces
– Three inbound windows plus a configuration window on PCI
– Four inbound windows
– Four outbound windows plus default translation for PCI
DDR memory controller
— Programmable timing supporting first generation DDR SDRAM
— 64-bit data interface, up to MHz data rate
— Four banks of memory supported, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports
— Full ECC support
— Page mode support (up to 16 simultaneous open pages)
— Contiguous or discontiguous memory mapping
— Sleep mode support for self refresh DDR SDRAM
— Supports auto refreshing
— On-the-fly power management using CKE signal
— Registered DIMM support
— Fast memory access via JTAG port
— 2.5-V SSTL2 compatible I/O
Programmable interrupt controller (PIC)
— Programming model is compliant with the OpenPIC architecture
— Supports 16 programmable interrupt and processor task priority levels
— Supports 12 discrete external interrupts
— Supports 4 message interrupts with 32-bit messages
相关PDF资料
PDF描述
MPC8555ECVTAQFX 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783
MPC8555EVTAQFX 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783
MPC8555ECPXAKDX 32-BIT, 600 MHz, RISC PROCESSOR, PBGA783
MPC8555PXALFX 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
MPC8555EVTAPDX 32-BIT, 833 MHz, RISC PROCESSOR, PBGA783
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