参数资料
型号: MPC8560PXAQFC
厂商: Freescale Semiconductor
文件页数: 70/108页
文件大小: 0K
描述: MPU POWERQUICC III 783FCPBGA
标准包装: 36
系列: MPC85xx
处理器类型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
电压: 1.3V
安装类型: 表面贴装
封装/外壳: 784-BBGA,FCBGA
供应商设备封装: 783-FCPBGA(29x29)
包装: 托盘
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
64
Freescale Semiconductor
RapidIO
The compliance of driver output signals TD[0:15] and TFRAME with their minimum data valid window
(DV) specification shall be determined by generating an eye pattern for each of the data signals and
comparing the eye pattern of each data signal with the RapidIO transmit mask shown in Figure 44. The
value of X2 used to construct the mask shall be (1 – DVmin)/2. A signal is compliant with the data valid
window specification if the transmit mask can be positioned on the signal’s eye pattern such that the eye
pattern falls entirely within the unshaded portion of the mask.
Figure 44. RapidIO Transmit Mask
Table 50. RapidIO Driver AC Timing Specifications—1 Gbps Data Rate
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Differential output high voltage
VOHD
200
540
mV
1
Differential output low voltage
VOLD
–540
–200
mV
1
Duty cycle
DC
48
52
%
2, 6
VOD rise time, 20%–80% of peak to peak
differential signal swing
tFALL
100
ps
3, 6
VOD fall time, 20%–80% of peak to peak
differential signal swing
tRISE
100
ps
6
Data valid
DV
575
ps
6
Skew of any two data outputs
tDPAIR
100
ps
4, 6
Skew of single data outputs to associated clock
tSKEW,PAIR
–100
100
ps
5, 6
Notes:
1.See Figure 44.
2.Requires ±100 ppm long term frequency stability.
3.Measured at VOD = 0 V.
4.Measured using the RapidIO transmit mask shown in Figure 44.
5.See Figure 49.
6.Guaranteed by design.
X2
VOHDmax
0
VOHDmin
VOLDmax
VOLDmin
1–X2
DV
V
OD
(m
V
)
Time (UI)
01
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