- 您现在的位置：买卖IC网 > PDF目录45372 > MPC8569VTANKGB (FREESCALE SEMICONDUCTOR INC) RISC PROCESSOR, PBGA783 PDF资料下载
参数资料
| 型号： | MPC8569VTANKGB |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | RISC PROCESSOR, PBGA783 |
| 封装： | 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783 |
| 文件页数： | 56/126页 |
| 文件大小： | 2847K |
| 代理商： | MPC8569VTANKGB |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页当前第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页
Pinout List
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
35
XGND
W23
SerDes Transceiver
Pad GND
——
XGND
Y21
SerDes Transceiver
Pad GND
——
AGND_SRDS
U25
SerDes PLL GND
—
Notes:
1. All multiplexed signals are listed only once and do not reoccur.
2. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the
reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k
Ωpull-down resistor. However, if the
signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at
reset, then a pull-up or active driver is needed.
3. When configured as I2C, this pin is an open drain signal and recommend a pull-up resistor (1 k
Ω) be placed on this pin to
OVDD. When configured as SD, this pin is not open drain and does not require a pull-up.
4. This pin has a weak internal pull-up resistor (~20 k
Ω).
5. This pin is an open drain signal.
6. Recommend a weak pull-up resistor (2–10 k
Ω) be placed on this pin to OVDD.
7. This pin requires a 200-
Ω pull-down to ground.
8. Do not connect.
9. Recommend a weak pull-down resistor (2–10 k
Ω) be placed on this pin to GND.
10. These are test signals for factory use only and must be pulled up (100
Ω–1 kΩ) to OVDD for normal machine operation.
11. These pins must not be pulled down during power-on reset.
12. See AN4232 MPC8569E PowerQUICC III Design Checklist for the required PLL filters to be attached to the AVDD pin.
13. These pins are connected to the VDD/GND planes internally and may be used by the core power supply to improve tracking
and regulation.
14. This pin selects the voltage of eLBC interface (BVDD). This pin has internal weak pull down.
15. This pin selects the voltage of UCC1 and UCC3 interfaces (LVDD1). This pin has internal weak pull down.
16. This pin selects the voltage of UCC2 and UCC4 interfaces (LVDD2). This pin has internal weak pull down.
17. This pin requires a 100-
Ω pull down to ground.
18. The value of LA[24:27] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-k
Ωpull-up or pull-down
resistors. See AN4232 MPC8569E PowerQUICC III Design Checklist for more details.
19. The value of QE_PE[27:29] during reset sets the DDR clock PLL settings. These pins require 4.7-k
Ω pull up or pull down
resistors. See AN4232 MPC8569E PowerQUICC III Design Checklist for more details.
20. The value of LALE, LGPL2/LOE/LFRE and LBCTL at reset set the e500 core clock to CCB Clock PLL ratio. These pins
require 4.7-k
Ωpull-up or pull-down resistors. See the AN4232 MPC8569E PowerQUICC III Design Checklist for more details.
21. The value of LCS[3:7] at reset sets the QE PLL settings. These pins require 4.7-k
Ω pull up or pull down resistors. See
AN4232 MPC8569E PowerQUICC III Design Checklist for more details.
22. The value of QE_PB[27:28], QE_PC4 and QE_PD4 at reset sets the Boot ROM location. These pins require 4.7-k
Ω pull up
or pull down resistors. See the MPC8569E PowerQUICC III Integrated Host Processor Family Reference Manual for details
23. These pins are sampled at reset for general-purpose configuration use by software. The value of LAD[0:15] at reset sets the
upper 16 bits of the GPPORCR
24. These pins must not be pulled up during power-on reset.
25. This output is actively driven during reset rather than being three-stated during reset.
Table 1. MPC8569E Pinout Listing (continued)
Signal1
Package Pin Number
Pin Type
Power Supply
Note
相关PDF资料 |
PDF描述 |
|---|---|
| MPC8569EVTAUNLB | RISC PROCESSOR, PBGA783 |
| MPC8569ECVTANKGB | RISC PROCESSOR, PBGA783 |
| MPC8569ECVTANKG | RISC PROCESSOR, PBGA783 |
| MPC8569VTAUNLA | RISC PROCESSOR, PBGA783 |
| MPC8569EVTAUNL | RISC PROCESSOR, PBGA783 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8569VTAQLJB | 功能描述:数字信号处理器和控制器 - DSP, DSC 8569 ST 1067/667/533 r2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| MPC8569VTAUNLB | 功能描述:数字信号处理器和控制器 - DSP, DSC 8569 ST 1333/667/533 r2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| MPC8572CLVTAULD | 功能描述:微处理器 - MPU 1333 LOW PWR EXT TEMP RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8572CLVTAULE | 功能描述:微处理器 - MPU R211 NoE NoPb 1333LP Ext RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8572CLVTAVND | 功能描述:微处理器 - MPU 1500 ExtTmp LwPwr RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
发布紧急采购，3分钟左右您将得到回复。