参数资料
型号: MPC8569VTAQLJB
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: RISC PROCESSOR, PBGA783
封装: 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
文件页数: 97/126页
文件大小: 2847K
代理商: MPC8569VTAQLJB
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Ethernet Interface
Freescale Semiconductor
72
2.6.5
QUICC Engine Block IEEE 1588 AC Specifications
The following table provides the QUICC Engine block IEEE 1588 AC timing specifications.
The following figure shows the data and command output AC timing diagram.
1QUICC Engine block IEEE 1588 Output AC timing: The output delay is counted starting at the rising
edge if tT11588CLKOUT is non-inverting. Otherwise, it is counted starting at the falling edge.
Figure 31. QUICC Engine Block IEEE 1588 Output AC Timing
Table 40. QUICC Engine Block IEEE 1588 AC Timing Specifications
Parameter
Symbol
Min
Typ
Max
Unit
Notes
QE_1588_CLK clock period
tT1588CLK
3.8
TRX_CLK × 7
ns
1, 3
QE_1588_CLK duty cycle
tT1588CLKH/
tT1588CLK
40
50
60
%
5
QE_1588_CLK peak-to-peak jitter
tT1588CLKINJ
——
250
ps
5
Rise time QE_1588_CLK (20%–80%)
tT1588CLKINR
1.0
2.0
ns
5
Fall time QE_1588_CLK (80%–20%)
tT1588CLKINF
1.0
2.0
ns
5
QE_1588_CLK_OUT clock period
tT1588CLKOUT
2×tT1588CLK
——
ns
QE_1588_CLK_OUT duty cycle
tT1588CLKOTH/
tT1588CLKOUT
30
50
70
%
QE_1588_PPS_OUT
tT1588OV
0.5
4.0
ns
QE_1588_TRIG_IN pulse width
tT1588TRIGH
2×tT1588CLK_
MAX
——
ns
2
QE_PTP_SOF_TX_IN pulse width
tT1588TRIGH
TTX_CLK ×2
ns
4
QE_PTP_SOF_RX_IN pulse width
tT1588TRIGH
TRX_CLK ×2
ns
4
Notes:
1. TRX_CLK is the max clock period of the QUICC Engine block’s receiving clock selected by TMR_CTRL[CKSEL]. See the
QUICC Engine Block with Protocol Interworking Reference Manual, for a description of TMR_CTRL registers.
2. It needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the QUICC Engine Block
with Protocol Interworking Reference Manual, for a description of TMR_CTRL registers.
3. The maximum value of tT1588CLK is not only defined by the value of tRX_CLK, but also defined by the recovered clock. For
example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK are 2800, 280, and 56 ns, respectively.
4. The minimum value of tTX/RXCLK is defined by the recovered clock. For example, for 10/100/1000 Mbps modes, the value of
tTX/RXCLK are 800, 80, and 16 ns, respectively.
5. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
QE_1588_CLK_OUT
QE_1588_PPS_OUT
tT1588OV
tT1588CLKOUT
tT1588CLKOUTH
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