参数资料
型号: MPC8572ECVTAVNB
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA1023
封装: 33 X 33 MM, LEAD FREE, PLASTIC, FCBGA-1023
文件页数: 116/138页
文件大小: 1502K
代理商: MPC8572ECVTAVNB
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
79
High-Speed Serial Interfaces (HSSI)
MPC8572E SerDes reference clock input’s DC requirement, AC-coupling has to be used. Figure 50
assumes that the LVPECL clock driver’s output impedance is 50
Ω. R1 is used to DC-bias the LVPECL
outputs prior to AC-coupling. Its value could be ranged from 140
Ω to 240Ω depending on clock driver
vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-
Ω termination
resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8572E SerDes
reference clock’s differential input amplitude requirement (between 200mV and 800mV differential peak).
For example, if the LVPECL output’s differential peak is 900mV and the desired SerDes reference clock
input amplitude is selected as 600mV, the attenuation factor is 0.67, which requires R2 = 25
Ω. Please
consult clock driver chip manufacturer to verify whether this connection scheme is compatible with a
particular clock driver chip.
Figure 50. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
50
Ω
50
Ω
SD
n_REF_CLK
SD
n_REF_CLK
Clock Driver
100
Ω differential PWB trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
LVPECL CLK
Driver Chip
R2
R1
MPC8572E
R1
10nF
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