参数资料
型号: MPC8572VTARNB
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 1067 MHz, MICROPROCESSOR, PBGA1023
封装: 33 X 33 MM, LEAD FREE, PLASTIC, FCBGA-1023
文件页数: 50/138页
文件大小: 1502K
代理商: MPC8572VTARNB
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
19
RESET Initialization
For example, if the platform (CCB) frequency is 533 MHz, the FIFO TX/RX clock frequency
should be no more than 127 MHz.
For 8-bit Encoded FIFO mode:
FIFO TX/RX clock frequency <= platform clock (CCB) frequency/3.2
For example, if the platform (CCB) frequency is 533 MHz, the FIFO TX/RX clock frequency
should be no more than 167 MHz.
4.6
Other Input Clocks
For information on the input clocks of other functional blocks of the platform such as SerDes and eTSEC,
see the respective sections of this document.
5
RESET Initialization
Table 8 describes the AC electrical specifications for the RESET initialization timing.
Table 9 provides the PLL lock times.
Table 8. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET
100
μs2
Minimum assertion time for SRESET
3
SYSCLKs
1
PLL config input setup time with stable SYSCLK before HRESET
negation
100
μs—
Input setup time for POR configs (other than PLL config) with respect to
negation of HRESET
4
SYSCLKs
1
Input hold time for all POR configs (including PLL config) with respect to
negation of HRESET
2
SYSCLKs
1
Maximum valid-to-high impedance time for actively driven POR configs
with respect to negation of HRESET
5
SYSCLKs
1
Notes:
1. SYSCLK is the primary clock input for the MPC8572E.
2. Reset assertion timing requirements for DDR3 DRAMs may differ.
Table 9. PLL Lock Times
Parameter/Condition
Symbol
Min
Typical
Max
PLL lock times
100
μs—
Local bus PLL
50
μs—
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