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参数资料
| 型号： | MPC9331FAR2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, PLASTIC, LQFP-32 |
| 文件页数： | 1/10页 |
| 文件大小： | 149K |
| 代理商： | MPC9331FAR2 |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9331/D
Rev 4, 02/2003
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
88
3.3V 1:6 LVCMOS PLL Clock
Generator
The MPC9331 is a 3.3V compatible, 1:6 PLL based clock generator
targeted for high performance low-skew clock distribution in mid-range to
high-performance telecom, networking, and computing applications. With
output frequencies up to 240 MHz and output skews less than 150 ps, the
device meets the needs of most the demanding clock applications. The
MPC9331 is specified for the temperature range of 0
°C to +70°C.
Features
1:6 PLL based low-voltage clock generator
3.3V power supply
Generates clock signals up to 240 MHz
Maximum output skew of 150 ps
Differential LVPECL reference clock input
Alternative LVCMOS PLL reference clock input
Internal and external PLL feedback
Supports zero-delay operation in external feedback mode
PLL multiplies the reference clock by 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2,
x/3 or x/4
Synchronous output clock stop in logic low eliminates output runt pulses
Power_down feature reduces output clock frequency
Drives up to 12 clock lines
32 lead LQFP packaging
Ambient temperature range 0°C to +70°C
Internal Power–Up Reset
Pin and function compatible to the MPC931
Functional Description
The MPC9331 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
MPC9331 requires either the selection of internal PLL feedback or the connection of one of the device outputs to the feedback
input to close the PLL feedback path in external feedback mode. The reference clock frequency and the divider for the feedback
path determine the VCO frequency. Both must be selected to match the VCO frequency range. In external PLL feedback
configuration and with the available post-PLL dividers (divide-by-2, divide-by-4, and divide-by-6), the internal VCO of the
MPC9331 is running at either 2x, 4x, 6x, 8x, or 12x of the reference clock frequency. In internal feedback configuration (divide-
by-8) the internal VCO is running 8x of the reference frequency. The frequency of the QA, QB, QC output banks is a division of the
VCO frequency and can be configured independently for each output bank using the FSELA, FSELB, and FSELC pins, respec-
tively. The available output to input frequency ratios are 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3, or x/4.
The REF_SEL pin selects the differential LVPECL or the LVCMOS compatible input as the reference clock signal. The
PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference
clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency
specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) by deasserting the
OE/MR pin. In the PLL configuration with external feedback selected, deasserting OE/MR causes the PLL to loose lock due to
missing feedback signal presence at FB_IN. Asserting OE/MR will enable the outputs and close the phase locked loop, enabling
the PLL to recover to normal operation. The MPC9331 output clock stop control allows the outputs to start and stop synchronous-
ly in logic low state, without the potential generation of runt pulses.
The MPC9331 is fully 3.3V compatible and requires no external loop filter components. The inputs (except PCLK) accept
LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
W
transmission lines. For series terminated transmission lines, each of the MPC9331 outputs can drive one or two traces giving the
devices an effective fanout of 1:12. The device is packaged in a 7x7 mm2 32-lead LQFP package.
2
FA SUFFIX
32 LEAD LQFP PACKAGE
CASE 873A
MPC9331
LOW VOLTAGE
3.3V LVCMOS 1:6
CLOCK GENERATOR
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9350 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC9350AC | 功能描述:时钟驱动器及分配 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MPC9350ACR2 | 功能描述:时钟发生器及支持产品 FSL 1-9 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9350D | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC9350FA | 功能描述:时钟驱动器及分配 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
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