- 您现在的位置：买卖IC网 > PDF目录26838 > MPC9352ACR2 (INTEGRATED DEVICE TECHNOLOGY INC) 9352 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 PDF资料下载
参数资料
| 型号： | MPC9352ACR2 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9352 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | LEAD FREE, LQFP-32 |
| 文件页数： | 1/16页 |
| 文件大小： | 346K |
| 代理商： | MPC9352ACR2 |
MPC9352
Rev. 6, 1/2005
Freescale Semiconductor
Technical Data
Freescale Confidential Proprietary, NDA Required / Preliminary
Freescale Semiconductor, Inc., 2005. All rights reserved.
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
3.3 V/2.5 V 1:11 LVCMOS Zero
Delay Clock Generator
The MPC9352 is a 3.3 V or 2.5 V compatible, 1:11 PLL based clock generator
targeted for high performance clock tree applications. With output frequencies up
to 200 MHz and output skews lower than 200 ps, the device meets the needs of
most demanding clock applications.
Features
Configurable 11 outputs LVCMOS PLL clock generator
Fully integrated PLL
Wide range of output clock frequency of 16.67 MHz to 200 MHz
Multiplication of the input reference clock frequency by 3, 2, 1, 3
÷ 2, 2 ÷ 3,
1
÷ 3 and 1 ÷ 2
2.5 V and 3.3 V LVCMOS compatible
Maximum output skew of 200 ps
Supports zero-delay applications
Designed for high-performance telecom, networking and computing
applications
32-lead LQFP package
32-lead Pb-free Package Available
Ambient Temperature Range –40°C to +85°C
Functional Description
The MPC9352 is a fully 3.3 V or 2.5 V compatible PLL clock generator and
clock driver. The device has the capability to generate output clock signals of
16.67 to 200 MHz from external clock sources. The internal PLL is optimized for
its frequency range and does not require external lock filter components. One output of the MPC9352 has to be connected to the
PLL feedback input FB_IN to close the external PLL feedback path. The output divider of this output setting determines the PLL
frequency multiplication factor. This multiplication factor, F_RANGE, and the reference clock frequency must be selected to sit-
uate the VCO in its specified lock range. The frequency of the clock outputs can be configured individually for all three output
banks by the FSELx pins supporting systems with different, but phase-aligned, clock frequencies.
The PLL of the MPC9352 minimizes the propagation delay, and therefore, supports zero-delay applications. All inputs and out-
puts are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50
transmission lines. Alternatively, each
output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.
The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The
MPC9352 is packaged in a 32 ld LQFP.
MPC9352
LOW VOLTAGE
3.3 V/2.5 V LVCMOS 1:11
CLOCK GENERATOR
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
相关PDF资料 |
PDF描述 |
|---|---|
| MPC93H51FA | PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC93H51FAR2 | PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC93R52ACR2 | 93R SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC93R52AC | 93R SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC940FA | MPC900 SERIES, LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9352FA | 功能描述:锁相环 - PLL 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| MPC9352FAR2 | 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Generator Single 32-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel |
| MPC93H51AC | 功能描述:时钟发生器及支持产品 FSL 1-9 LVCMOS/LVPEC L to LVCMOS PLL Cloc RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC93H51ACR2 | 功能描述:时钟发生器及支持产品 FSL 1-9 LVCMOS/LVPEC L to LVCMOS PLL Cloc RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC93H51FA | 功能描述:IC PLL CLK DVR HI-DRIVE 32-LQFP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
发布紧急采购，3分钟左右您将得到回复。