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| 型号： | MPC9352ACR2 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9352 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | LEAD FREE, LQFP-32 |
| 文件页数： | 15/16页 |
| 文件大小： | 346K |
| 代理商： | MPC9352ACR2 |
Advanced Clock Drivers Devices
8
Freescale Semiconductor
MPC9352
APPLICATIONS INFORMATION
Programming the MPC9352
The MPC9352 supports output clock frequencies from
16.67 to 200 MHz. Different feedback and output divider
configurations can be used to achieve the desired input to
output frequency relationship. The feedback frequency and
divider should be used to situate the VCO in the frequency
lock range between 200 and 400 MHz for stable and optimal
operation. The FSELA, FSELB, FSELC pins select the
desired output clock frequencies. Possible frequency ratios
of the reference clock input to the outputs are 1:1, 1:2, 1:3,
illustrates the various output configurations and frequency
ratios supported by the MPC9352. See also Figure 3 to
used for feedback.
Table 9. MPC9352 Example Configuration (F_RANGE = 0)
PLL
Feedback
fref(1) [MHz]
1. fref is the input clock reference frequency (CCLK).
FSELA
FSELB
FSELC
QA[0:4]:fref ratio
QB[0:3]:fref ratio
QC[0:1]:fref ratio
VCO
÷ 4(2)
2. QAx connected to FB_IN and FSELA=0.
50-100
0
fref
(50-100 MHz)
fref
(50-100 MHz)
fref * 2 (100-200 MHz)
0
1
fref
(50-100 MHz)
fref
(50-100 MHz)
fref
(50-100 MHz)
1
0
fref * 2
÷3 (33-66 MHz) fref
(50-100 MHz)
fref * 2 (100-200 MHz)
1
0
1
fref * 2
÷3 (33-66 MHz) fref
(50-100 MHz)
fref
(50-100 MHz)
VCO
÷ 6(3)
3. QAx connected to FB_IN and FSELA=1.
33.3-66.67
1
0
fref
(33-66 MHz)
fref * 3
÷2 (50-100 MHz) fref * 3 (100-200 MHz)
1
0
1
fref
(33-66 MHz)
fref * 3
÷2 (50-100 MHz) fref * 3÷2 (50-100 MHz)
1
0
fref
(33-66 MHz)
fref * 3 (100-200 MHz)
1
fref
(33-66 MHz)
fref * 3 (100-200 MHz)
fref * 3
÷2 (50-100 MHz)
Table 10. MPC9352 Example Configurations (F_RANGE = 1)
PLL Feedback
fref(1) [MHz]
1. fref is the input clock reference frequency (CCLK).
FSELA
FSELB
FSELC
QA[0:4]:fref ratio
QB[0:3]:fref ratio
QC[0:1]:fref ratio
VCO
÷ 8(2)
2. QAx connected to FB_IN and FSELA=0.
25-50
0
fref
(25-50 MHz)
fref
(25-50 MHz)
fref * 2
(50-100 MHz)
0
1
fref
(25-50 MHz)
fref
(25-50 MHz)
fref
(25-50 MHz)
1
0
fref * 2
÷3 (16-33 MHz) fref
(25-50 MHz)
fref * 2
(50-100 MHz)
1
0
1
fref * 2
÷3 (16-33 MHz) fref
(25-50 MHz)
fref
(25-50 MHz)
VCO
÷ 12(3)
3. QAx connected to FB_IN and FSELA=1.
16.67-33.3
1
0
fref
(16-33 MHz)
fref * 3
÷2 (25-50 MHz) fref * 3 (50-100 MHz)
1
0
1
fref
(16-33 MHz)
fref * 3
÷2 (25-50 MHz) fref * 3÷2 (25-50 MHz)
1
0
fref
(16-33 MHz)
fref * 3
(50-100 MHz) fref * 3
(50-100 MHz)
1
fref
(16-33 MHz)
fref * 3
(50-100 MHz) fref * 3
÷2 (25-50 MHz)
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