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| 型号： | MPC93H52ACR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 93H SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | LEAD FREE, LQFP-32 |
| 文件页数： | 13/16页 |
| 文件大小： | 322K |
| 代理商： | MPC93H52ACR2 |
Advanced Clock Drivers Devices
6
Freescale Semiconductor
MPC93H52
APPLICATIONS INFORMATION
Programming the MPC93H52
The MPC93H52 supports output clock frequencies from
16.67 to 240 MHz. Different feedback and output divider
configurations can be used to achieve the desired input to
output frequency relationship. The feedback frequency and
divider should be used to situate the VCO in the frequency
lock range between 200 and 480 MHz for stable and optimal
operation. The FSELA, FSELB, FSELC pins select the
desired output clock frequencies. Possible frequency ratios
of the reference clock input to the outputs are 1:1, 1:2, 1:3,
3:2 as well as 2:3, 3:1 and 2:1. Table 7 illustrates the various
output configurations and frequency ratios supported by the
MPC93H52. See also Table 8 and Figure 3 to Figure 6 for
further reference. A ÷2 output divider cannot be used for
feedback.
Table 7. MPC93H52 Example Configuration (F_RANGE = 0)
PLL
Feedback
fref(1)
[MHz]
1. fref is the input clock reference frequency (CCLK).
FSELA
FSELB
FSELC
QA[0:4]:fref ratio
QB[0:3]:fref ratio
QC[0:1]:fref ratio
VCO
÷ 4(2)
2. fref is the input clock reference frequency (CCLK).
50-120
0
fref
(50-120 MHz) fref
2
(100-240 MHz)
0
1
fref
(50-120 MHz) fref
(50-120 MHz)
1
0
fref
2÷3
(33-80 MHz) fref
(50-120 MHz) fref
2
(100-240 MHz)
1
0
1
fref
2÷3
(33-80 MHz) fref
(50-120 MHz) fref
(50-120 MHz)
VCO
÷ 6(3)
3. fref is the input clock reference frequency (CCLK).
33.3-80
1
0
fref
(33-80 MHz) fref
3÷2
(50-120 MHz) fref
3
(100-240 MHz)
1
0
1
fref
(33-80 MHz) fref
3÷2
(50-120 MHz) fref
3÷2
(50-120 MHz)
1
0
fref
(33-80 MHz) fref
3
(100-240 MHz) fref
3
(100-240 MHz)
1
fref
(33-80 MHz) fref
3
(100-240 MHz) fref
3÷2
(50-120 MHz)
Table 8. MPC93H52 Example Configurations (F_RANGE = 1)
PLL
Feedback
fref(1)
[MHz]
1. fref is the input clock reference frequency (CCLK).
FSELA
FSELB
FSELC
QA[0:4]:fref ratio
QB[0:3]:fref ratio
QC[0:1]:fref ratio
VCO
÷ 8(2)
2. QAx connected to FB_IN and FSELA=0.
25-60
0
fref
(25-60 MHz) fref
2
(50-120 MHz)
0
1
fref
(25-60 MHz) fref
(25-60 MHz)
100
fref
2÷3
(16-40 MHz) fref
(25-60 MHz) fref
2
(50-120 MHz)
101
fref
2÷3
(16-40 MHz) fref
(25-60 MHz) fref
(25-60 MHz)
VCO
÷ 12(3)
3. QAx connected to FB_IN and FSELA=1.
16.67-40
1
0
fref
(16-40 MHz) fref
3÷2
(25-60 MHz) fref
3
(50-120 MHz)
1
0
1
fref
(16-40 MHz) fref
3÷2
(25-60 MHz) fref
3÷2
(25-60 MHz)
1
0
fref
(16-40 MHz) fref
3
(50-120 MHz) fref
3
(50-120 MHz)
1
fref
(16-40 MHz) fref
3
(50-120 MHz) fref
3÷2
(25-60 MHz)
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| MPC93H52FAR2 | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel |
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| MPC93R51AC | 功能描述:时钟驱动器及分配 3.3V 240MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MPC93R51ACR2 | 功能描述:时钟发生器及支持产品 FSL 1-9 LVCMOS/LVPEC L to LVCMOS PLL Cloc RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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