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参数资料
| 型号： | MPC93R51ACR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 93R SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, LEAD FREE, LQFP-32 |
| 文件页数： | 8/12页 |
| 文件大小： | 339K |
| 代理商： | MPC93R51ACR2 |
Advanced Clock Drivers Devices
Freescale Semiconductor
5
MPC93R51
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0° to 70°C)(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequency(2)
÷ 4 feedback
÷ 8 feedback
Static test mode
2. The PLL will be unstable with a divide by 2 feedback rati,o
50
25
0
120
60
300
MHz
PLL_EN = 1
PLL_EN = 0
fVCO
VCO Frequency
200
480
MHz
fMAX
Maximum Output Frequency2
÷ 2 output
÷ 4 output
÷ 8 output
100
50
25
240
120
60
MHz
frefDC
Reference Input Duty Cycle
25
75
%
VPP
Peak-to-Peak Input Voltage
PCLK, PCLK
500
1000
mV
LVPECL
VCMR(3)
3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
Common Mode Range
PCLK, PCLK
1.2
VCC–0.9
V
LVPECL
tr, tf(4)
4. The MPC93R51 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t(), can only be guaranteed if tr/tf
are within the specified range.
TCLK Input Rise/Fall Time
1.0
ns
0.8 to 2.0 V
t()
Propagation Delay (static phase offset)
TCLK to EXT_FB
PCLK to EXT_FB
-50
+25
+150
+325
ps
PLL locked
tsk(o)
Output-to-Output Skew
150
ps
DC
Output Duty Cycle
100 – 240 MHz
50 – 120 MHz
25 – 60 MHz
45
47.5
48.75
50
55
52.5
51.75
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4 V
tPLZ, HZ
Output Disable Time
7.0
ns
tPZL, ZH
Output Enable Time
6.0
ns
BW
PLL closed loop bandwidth
÷ 4 feedback
÷ 8 feedback
3.0 – 9.5
1.2 – 2.1
MHz
–3 db point of
PLL transfer characteristic
tJIT(CC)
Cycle-to-cycle jitter
÷ 4 feedback
Single Output Frequency Configuration
10
22
ps
RMS value
tJIT(PER)
Period Jitter
÷ 4 feedback
Single Output Frequency Configuration
8.0
15
ps
RMS value
tJIT()
I/O Phase Jitter
4.0 – 17
ps
RMS value
tLOCK
Maximum PLL Lock Time
1.0
ms
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC93R51D | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC93R51FA | 功能描述:时钟驱动器及分配 3.3V 240MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MPC93R51FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK DRVR SGL 32LQFP - Tape and Reel |
| MPC93R52 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW VOLTAGE 3.3V LVCMOS 1:11 CLOCK GENERATOR |
| MPC93R52AC | 功能描述:时钟发生器及支持产品 FSL 1-11 LVCMOS PLL Clock Generator, pwr RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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