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参数资料
| 型号： | MPC951FA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 951 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, PLASTIC, LQFP-32 |
| 文件页数： | 6/8页 |
| 文件大小： | 303K |
| 代理商： | MPC951FA |
MPC951
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
165
cy will add significantly to the measured jitter. The oscilloscope
cannot collect adjacent pulses, rather it collects data from a
very large sample of pulses. It is safe to assume that collecting
pulse information in this mode will produce jitter values some-
what larger than if consecutive cycles were measured, there-
fore, this measurement will represent an upper bound of
cycle–to–cycle jitter. Most likely, this is a conservative estimate
of the cycle–to–cycle jitter.
Figure 3. PLL Jitter and Edge Displacement
1
212
12
1
232
12
3
Peak-to-Peak PLL Jitter
Peak-to-Peak Period Jitter
Peak-to-Peak PLL Jitter
Peak-to-Peak Period Jitter
There are two sources of jitter in a PLL based clock driver,
the commonly known random jitter of the PLL and the less
intuitive jitter caused by synchronous, different frequency out-
puts switching. For the case where all of the outputs are
switching at the same frequency the total jitter is exactly equal
to the PLL jitter. In a device, like the MPC951, where a number
of the outputs can be switching synchronously but at different
frequencies a “multi–modal” jitter distribution can be seen on
the highest frequency outputs. Because the output being moni-
tored is affected by the activity on the other outputs it is impor-
tant to consider what is happening on those other outputs.
From Figure 3, one can see for each rising edge on the higher
frequency signal the activity on the lower frequency signal is
not constant. The activity on the other outputs tends to alter the
internal thresholds of the device such that the placement of the
edge being monitored is displaced in time. Because the signals
are synchronous the relationship is periodic and the resulting
jitter is a compilation of the PLL jitter superimposed on the dis-
placed edges. When histograms are plotted the jitter looks like
a “multi–modal” distribution as pictured in Figure 3. Depending
on the size of the PLL jitter and the relative displacement of the
edges the “multi–modal” distribution will appear truly “multi–
modal” or simply like a “fat” Gaussian distribution. Again note
that in the case where all the outputs are switching at the same
frequency there is no edge displacement and the jitter is re-
duced to that of the PLL.
Figure 4 graphically represents the PLL jitter of the
MPC951. The data was taken for several different output con-
figurations. By triggering on the lowest frequency output the
PLL jitter can be measured for configurations in which outputs
are switching at different frequencies. As one can see in the
figure the PLL jitter is much less dependent on output configu-
ration than on internal VCO frequency.
Figure 4. RMS PLL Jitter versus VCO Frequency
0
5
10
15
20
25
30
35
40
160
240
320
400
480
560
Conf 1
Conf 2
Conf 3
Conf 1 = All Outputs at the Same Frequency
Conf 2 = 4 Outputs at X, 5 Outputs at X/2
Conf 3 = 1 Output at X, 8 Outputs at X/4
VCO Frequency (MHz)
RMS
Jitter
(ps)
Figure 5. Peak–to–Peak Period Jitter versus
VCO Frequency
150
200
250
300
350
400
160
240
320
400
480
560
Conf 2
Conf 3
Conf 2 = 4 Outputs at X, 5 Outputs at X/2
Conf 3 = 1 Output at X, 8 Outputs at X/4
VCO Frequency (MHz)
Paek-to-Peak
Jitter
(ps)
Two different configurations were chosen to look at the peri-
od displacement caused by the switching outputs. Configura-
tion 3 is considered worst case as the “trimodal” distribution
(as pictured in Figure 3) represents the largest spread be-
tween distribution peaks. Configuration 2 is considered a typi-
cal configuration with half the outputs at a high frequency and
the remaining outputs at one half the high frequency. For these
cases the peak–to–peak numbers are reported in Figure 5 as
2
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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