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| 型号： | MPC954DTR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 954 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封装： | TSSOP-24 |
| 文件页数： | 1/5页 |
| 文件大小： | 291K |
| 代理商： | MPC954DTR2 |
5
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MPC954/D
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
457
Low Voltage PLL Clock Driver
The MPC954 is a 3.3V compatible, PLL based zero delay buffer tar-
geted for high performance clock tree designs. With 11 outputs at fre-
quencies of up to 100MHz and output skews of 200ps the MPC954 is
ideal for the most demanding clock tree designs. The devices employ a
fully differential PLL design to minimize cycle–to–cycle and phase jitter.
Fully Integrated PLL
Output Frequency up to 100MHz
Outputs Disable in High Impedance
TSSOP Packaging
50ps Cycle–to–Cycle Jitter Typical
The analog VCC pin of the device also serves as a PLL bypass select
pin. When driven low the VCCA pin will route the REF_CLK input around
the PLL directly to the outputs. The OE input is a logic enable for all of the
outputs except QFB. A low on the OE pin forces Q0–Q9 to a logic low
state.
The MPC954 is fully 3.3V compatible and requires no external loop
filter components. All inputs accept LVCMOS or LVTTL compatible levels
while the outputs provide LVCMOS levels with the ability to drive termi-
nated 50
transmission lines. The output impedance of the MPC954 is
10
W, therefore for series terminated 50 lines, each of the MPC954 out-
puts can drive two traces giving the device an effective fanout of 1:22.
The device is packaged in a 24–lead TSSOP package to provide the
optimum combination of board density and performance.
Figure 1. Block Diagram
REF_CLK
FB_CLK
PLL
VCCA
Q0
Q9
QFB
OE
(Int pull down)
Rev 1
MPC954
LOW VOLTAGE
PLL ZERO DELAY BUFFER
DT SUFFIX
24–LEAD TSSOP PACKAGE
CASE 948H
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For More Information On This Product,
Go to: www.freescale.com
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