- 您现在的位置：买卖IC网 > PDF目录26839 > MPC9608ACR2 (INTEGRATED DEVICE TECHNOLOGY INC) 9608 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 PDF资料下载
参数资料
| 型号： | MPC9608ACR2 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9608 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, LEAD FREE, PLASTIC, LQFP-32 |
| 文件页数： | 1/12页 |
| 文件大小： | 315K |
| 代理商： | MPC9608ACR2 |
MPC9608
Rev 4, 10/2004
Freescale Semiconductor
Technical Data
Freescale Semiconductor, Inc., 2004. All rights reserved.
1:10 LVCMOS Zero Delay
Clock Buffer
The MPC9608 is a 3.3 V compatible, 1:10 PLL based zero-delay buffer. With
a very wide frequency range and low output skews the MPC9608 is targeted for
high performance and mid-range clock tree designs.
Features
1:10 outputs LVCMOS zero-delay buffer
Single 3.3 V supply
Supports a clock I/O frequency range of 12.5 to 200 MHz
Selectable divide-by-two for one output bank
Synchronous output enable control (CLK_STOP)
Output tristate control (output high impedance)
PLL bypass mode for low frequency system test purpose
Supports networking, telecommunications and computer applications
Supports a variety of microprocessors and controllers
Compatible to PowerQuicc I and II
Ambient Temperature Range -40
°C to +85°C
32-lead Pb-free Package Available
Functional Description
The MPC9608 uses an internal PLL and an external feedback path to lock its
low-skew clock output phase to the reference clock phase, providing virtually
zero propagation delay. This enables nested clock designs with near-zero
insertion delay. Designs using the MPC9608 as PLL fanout buffer will show
significantly lower clock skew than clock distributions developed from traditional
fanout buffers. The device offers one reference clock input and two banks of 5 outputs for clock fanout. The input frequency and
phase is reproduced by the PLL and provided at the outputs. A selectable frequency divider sets the bank B outputs to generate
either an identical copy of the bank A clocks or one half of the bank A clock frequency. Both output banks remain synchronized
to the input reference for both bank B configurations.
Outputs are only disabled or enabled when the outputs are already in logic low state (CLK_STOP). For system test and
diagnosis, the MPC9608 outputs can also be set to high-impedance state by connecting OE to logic high level. Additionally, the
device provides a PLL bypass mode for low frequency test purpose. In PLL bypass mode, the minimum frequency and static
phase offset specification do not apply.
CLK_STOP and OE do not affect the PLL feedback output (QFB) and down stream clocks can be disabled without the internal
PLL losing lock.
The MPC9608 is fully 3.3 V compatible and requires no external components for the internal PLL. All inputs accept LVCMOS
signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
transmission lines on
the incident edge. For series terminated transmission lines, each of the MPC9608 outputs can drive one or two traces giving the
devices an effective fanout of 1:20. The device is packaged in a 7x7 mm2 32-lead LQFP package.
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
MPC9608
LOW VOLTAGE 3.3 V
LVCMOS 1:10 ZERO-DELAY
CLOCK BUFFER
相关PDF资料 |
PDF描述 |
|---|---|
| MPC9608FAR2 | 9608 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9608AC | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC961CFAR2 | 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC961CFA | 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC961CAC | 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9608FA | 功能描述:时钟缓冲器 3.3V 200MHz Clock Generator RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| MPC9608FAR2 | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK BFFR SGL 32LQFP - Tape and Reel |
| MPC961C | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW VOLTAGE ZERO DELAY BUFFER |
| MPC961CAC | 功能描述:时钟缓冲器 RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| MPC961CACR2 | 功能描述:IC BUFFER ZD 1:18 PLL 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
发布紧急采购，3分钟左右您将得到回复。