参数资料
型号: MPC9608ACR2
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: 9608 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封装: 7 X 7 MM, LEAD FREE, PLASTIC, LQFP-32
文件页数: 12/12页
文件大小: 315K
代理商: MPC9608ACR2
Advanced Clock Drivers Device Data
Freescale Semiconductor
9
MPC9608
Figure 9. Output-to-Output Skew tSK(O)
The pin-to-pin skew is defined as the worst case difference in propagation delay between
any similar delay path within a single device.
VCC
VCC ÷ 2
GND
VCC
VCC ÷ 2
GND
tSK(O)
VCC
VCC ÷ 2
GND
VCC
VCC ÷ 2
GND
t()
CCLK
FB_IN
Figure 10. Propagation Delay (tPD, static phase offset)
Test Reference
The time from the PLL controlled edge to the non controlled edge, divided by the time between
PLL controlled edges, expressed as a percentage.
VCC
VCC ÷ 2
GND
tP
T0
DC = tP/T0 x 100%
Figure 11. Output Duty Cycle (DC)
Figure 12. I/O Jitter
The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample
of cycles.
TJIT() = |T0 - T1 mean|
CCLK
FB_IN
Figure 13. Cycle-to-Cycle Jitter
The variation in cycle time of a signal between adjacent cycles, over a random sample of
adjacent cycle pairs.
TN
TJIT(CC) = |TN -TN + 1|
TN + 1
Figure 14. Period Jitter
The deviation in cycle time of a signal with respect to the ideal period over a random sample
of cycles.
TJIT(PER) = |TN - 1/f0|
T0
Figure 15. Output Transition Time Test Reference
tF
tR
VCC = 3.3 V
2.4
0.55
Figure 16. Setup and Hold Time (ts, tH) Test Reference
VCC
GND
ts
CCLK
CLK_STOP
VCC
GND
tH
VCC ÷ 2
相关PDF资料
PDF描述
MPC9608FAR2 9608 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC9608AC PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC961CFAR2 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC961CFA 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC961CAC 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
相关代理商/技术参数
参数描述
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MPC9608FAR2 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK BFFR SGL 32LQFP - Tape and Reel
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MPC961CAC 功能描述:时钟缓冲器 RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟(最大值): 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel
MPC961CACR2 功能描述:IC BUFFER ZD 1:18 PLL 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器,PLL,频率合成器 系列:- 标准包装:1,000 系列:- 类型:时钟/频率合成器,扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP(8x8) 包装:带卷 (TR) 其它名称:844S012AKI-01LFT