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参数资料
| 型号： | MPC954DT |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | MPC900 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封装： | TSSOP-24 |
| 文件页数： | 3/5页 |
| 文件大小： | 117K |
| 代理商： | MPC954DT |
5
MPC954
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
459
DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
VIH
Input HIGH Voltage
LVCMOS Inputs
2.0
3.6
V
VIL
Input LOW Voltage
LVCMOS Inputs
0.8
V
VOH
Output HIGH Voltage
2.4
V
IOH = –20mA, Note 1.
VOL
Output LOW Voltage
0.5
V
IOL = 20mA, Note 1.
IIN
Input Current
±120
A
Note 2.
CIN
Input Capacitance
4
pF
Cpd
Power Dissipation Capacitance
25
pF
Per Output
ICC
Maximum Quiescent Supply Current
40
mA
All VCC Pins
ICCPLL
Maximum PLL Supply Current
15
mA
VCCA Pin Only
1. The MPC954 outputs can drive series or parallel terminated 50
(or 50 to VCC/2) transmission lines on the incident edge
(see Applications Info section).
2. Inputs have pullup resistor which affect input current.
PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C)
Symbol
Characteristic
Min
Max
Unit
Condition
fref
Reference Input Frequency
50
100
MHz
frefDC
Reference Input Duty Cycle
25
75
%
AC CHARACTERISTICS (TA = 0°C to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
tr, tf
Output Rise/Fall Time
0.3
1.5
ns
0.8 to 2.0V, (Note 1.)
tpw
Output Duty Cycle
40
50
60
%
(Note 1.)
tsk(O)
Output–to–Output Skews
300
ps
(Note 1.)
fmax
Maximum Output Frequency
PLL Mode
50
100
MHz
(Note 1.)
tpd(lock)
REF_CLK to FB_CLK Delay (with PLL Locked)
–300
0
ps
(Note 1.)
tPLZ,HZ
Output Disable Time
7
ns
(Note 1.)
tPZL
Output Enable Time
7
ns
(Note 1.)
tjitter
Cycle–to–Cycle Jitter (Peak–to–Peak)
50
ps
(Note 1.)
tlock
Maximum PLL Lock Time
10
ms
1. Termination of 50
W to VCC/2.
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