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参数资料
| 型号： | MPC958 |
| 厂商： | Motorola, Inc. |
| 英文描述： | LOW VOLTAGE PLL CLOCK DRIVER |
| 中文描述： | 低压PLL时钟驱动器 |
| 文件页数： | 3/8页 |
| 文件大小： | 253K |
| 代理商： | MPC958 |
MPC958
ECLinPS and ECLinPS Lite
DL140 — Rev 3
MOTOROLA
DC CHARACTERISTICS
(TA = 0
°
to 70
°
C, VCC = 3.3V
±
5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
VIH
VIL
VPP
VCMR
VOH
VOL
IIN
CIN
Cpd
ICC
ICCPLL
1. VCMR is the center of the differential input signal. Normal operation is obtained when the input crosspoint is within the VCMR range and the input
swing lies within the VPP specification.
2. The MPC958 outputs can drive series or parallel terminated 50
(or 50
to VCC/2) transmission lines on the incident edge (see Applications
Info section).
Input HIGH Voltage LVCMOS Inputs
2.0
3.6
V
Input LOW Voltage LVCMOS Inputs
0.8
V
Peak–to–Peak Input Voltage
PECL_CLK
300
1000
mV
Common Mode Range
PECL_CLK
1.0
3.0
V
Note 1.
Output HIGH Voltage
2.4
V
IOH = –20mA, Note 2.
IOL = 20mA, Note 2.
Output LOW Voltage
0.5
V
Input Current
±
120
μ
A
Input Capacitance
4
pF
Power Dissipation Capacitance
25
pF
Per Output
Maximum Quiescent Supply Current
75
mA
All VCC Pins
Maximum PLL Supply Current
15
20
mA
VCCA Pin Only
PLL INPUT REFERENCE CHARACTERISTICS
(TA = 0 to 70
°
C)
Symbol
Characteristic
Min
Max
Unit
Condition
fref
frefDC
3. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.
Reference Input Frequency
Note 3.
Note 3.
MHz
Reference Input Duty Cycle
25
75
%
AC CHARACTERISTICS
(TA = 0
°
C to 70
°
C, VCC = 3.3V
±
5%
)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
tr, tf
Output Rise/Fall Time
0.10
1.0
ns
0.8 to 2.0V
Note 4.
tpw
Output Duty Cycle
PLL Mode
tcycle/2 –
400
tcycle/2 +
400
ps
Note 4.
tsk(O)
fVCO
fmax
Output–to–Output Skews (Relative to QFB)
200
ps
Note 4.
PLL VCO Lock Range
200
400
MHz
Maximum Output Frequency
(Note 4.)
PLL Mode
PLL Mode
Bypass Mode
50
100
100
200
200
MHz
VCO_SEL = ‘1’
VCO_SEL = ‘0’
tpd(lock)
tpd(bypass)
tPLZ,HZ
tPZL
tjitter
tlock
4. Termination of 50 to VCC/2.
Input to Ext_FB Delay (with PLL Locked @ 100MHz)
–70
130
ps
Note 4.
Input to Q Delay
3.0
7.0
ns
PLL Bypassed
Output Disable Time
7
ns
Output Enable Time
6
ns
Cycle–to–Cycle Jitter (Peak–to–Peak)
100
ps
Note 4.
Maximum PLL Lock Time
10
ms
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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