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参数资料
| 型号： | MPC9608 |
| 厂商： | Motorola, Inc. |
| 英文描述： | 1:10 LVCMOS Zero Delay Clock Buffer |
| 中文描述： | 1:10的LVCMOS零延迟时钟缓冲器 |
| 文件页数： | 1/12页 |
| 文件大小： | 423K |
| 代理商： | MPC9608 |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 2004
Order this document
by MPC9608
1:10 LVCMOS Zero Delay
Clock Buffer
The MPC9608 is a 3.3 V compatible, 1:10 PLL based zero-delay buffer. With a
very wide frequency range and low output skews the MPC9608 is targeted for
high performance and mid-range clock tree designs.
Features
1:10 outputs LVCMOS zero-delay buffer
Single 3.3 V supply
Supports a clock I/O frequency range of 12.5 to 200 MHz
Selectable divide-by-two for one output bank
Synchronous output enable control (CLK_STOP)
Output tristate control (output high impedance)
PLL bypass mode for low frequency system test purpose
Supports networking, telecommunications and computer applications
Supports a variety of microprocessors and controllers
Compatible to PowerQuicc I and II
Ambient Temperature Range -40
°
C to +85
°
C
32-lead Pb-free package available
Functional Description
The MPC9608 uses an internal PLL and an external feedback path to lock its
low-skew clock output phase to the reference clock phase, providing virtually zero
propagation delay. This enables nested clock designs with near-zero insertion
delay. Designs using the MPC9608 as PLL fanout buffer will show significantly lower clock skew than clock distributions developed
from traditional fanout buffers. The device offers one reference clock input and two banks of 5 outputs for clock fanout. The input
frequency and phase is reproduced by the PLL and provided at the outputs. A selectable frequency divider sets the bank B outputs
to generate either an identical copy of the bank A clocks or one half of the bank A clock frequency. Both output banks remain syn-
chronized to the input reference for both bank B configurations.
Outputs are only disabled or enabled when the outputs are already in logic low state (CLK_STOP). For system test and diagnosis,
the MPC9608 outputs can also be set to high-impedance state by connecting
OE
to logic high level. Additionally, the device provides
a PLL bypass mode for low frequency test purpose. In PLL bypass mode, the minimum frequency and static phase offset specification
do not apply.
CLK_STOP and
OE
do not affect the PLL feedback output (QFB) and down stream clocks can be disabled without the internal PLL
losing lock.
The MPC9608 is fully 3.3 V compatible and requires no external components for the internal PLL. All inputs accept LVCMOS sig-
nals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
transmission lines on the inci-
dent edge. For series terminated transmission lines, each of the MPC9608 outputs can drive one or two traces giving the devices an
effective fanout of 1:20. The device is packaged in a 7x7 mm
2
32-lead LQFP package.
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A
MPC9608
LOW VOLTAGE 3.3 V
LVCMOS 1:10 ZERO-DELAY
CLOCK BUFFER
AC SUFFIX
32 LEAD LQFP PACKAGE-Pb-free
CASE 873A
REV 2
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9608AC | 功能描述:时钟缓冲器 RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| MPC9608ACR2 | 功能描述:时钟缓冲器 RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| MPC9608FA | 功能描述:时钟缓冲器 3.3V 200MHz Clock Generator RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| MPC9608FAR2 | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK BFFR SGL 32LQFP - Tape and Reel |
| MPC961C | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW VOLTAGE ZERO DELAY BUFFER |
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