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参数资料
| 型号： | MPC9608 |
| 厂商： | Motorola, Inc. |
| 英文描述： | 1:10 LVCMOS Zero Delay Clock Buffer |
| 中文描述： | 1:10的LVCMOS零延迟时钟缓冲器 |
| 文件页数： | 7/12页 |
| 文件大小： | 423K |
| 代理商： | MPC9608 |
MPC9608
TIMING SOLUTIONS
7
Due to the statistical nature of I/O jitter, an RMS value (1
σ
)
is specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 8.
The feedback trace delay is determined by the board layout
and can be used to fine-tune the effective delay through each
device. In the following example calculation a I/O jitter confi-
dence factor of 99.7% (
±
3
σ
) is assumed, resulting in a worst
case timing uncertainty from input to any output of -295 ps to
295 ps
1
relative to CCLK:
t
SK(PP)
=
[-100 ps...100 ps] + [-150 ps...150 ps] +
[(15 ps
.
-3)...(15 ps
.
3)] + t
PD, LINE(FB)
t
SK(PP)
=
[-295 ps...295 ps] + t
PD, LINE(FB)
Driving Transmission Lines
The MPC9608 clock driver was designed to drive high
speed signals in a terminated transmission line environment. To
provide the optimum flexibility to the user the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of less than 20
the drivers can drive ei-
ther parallel or series terminated transmission lines. For more
information on transmission lines the reader is referred to Mo-
torola application note AN1091. In most high performance clock
networks point-to-point distribution of signals is the method of
choice. In a point-to-point scheme either series terminated or
parallel terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a 50
resistance to V
CC
÷
2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each output
of the MPC9608 clock driver. For the series terminated case
however there is no DC current draw, thus the outputs can drive
multiple series terminated lines. Figure 5 “Single versus Dual
Transmission Lines” illustrates an output driving a single series
terminated line versus two series terminated lines in parallel.
When taken to its extreme, the fanout of the MPC9608 clock
driver is effectively doubled due to its capability to drive multiple
lines.
The waveform plots in Figure 6 “Single versus Dual Line
Termination Waveforms” show the simulation results of an out-
put driving a single line versus two lines. In both cases the drive
capability of the MPC9608 output buffer is more than sufficient
to drive 50
transmission lines on the incident edge. From the
delay measurements in the simulations a delta of only 43 ps ex-
ists between the two differently loaded outputs. This suggests
that the dual line driving need not be used exclusively to main-
tain the tight output-to-output skew of the MPC9608. The output
waveform in Figure 6 “Single versus Dual Line Termination
Waveforms” shows a step in the waveform. This step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 36
series resistor plus the output
impedance does not match the parallel combination of the line
impedances. The voltage wave launched down the two lines will
equal:
V
L
= V
S
( Z
0
÷
(R
S
+ R
0
+ Z
0
))
Z
0
= 50
|| 50
R
S
= 36
|| 36
R
0
= 14
V
L
= 3.0 ( 25
÷
(18 + 17 + 25))
= 1.31 V
At the load end the voltage will double to 2.6 V due to the
near unity reflection coefficient. It will then increment towards
the quiescent 3.0 V in steps separated by one round trip delay
(in this case 4.0 ns).
TABLE 8. Confidence Facter CF
CF
±
1
σ
±
2
σ
±
3
σ
±
4
σ
±
5
σ
±
6
σ
Probability of clock edge within the distribution
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
1. Skew data are designed targets and pending device specifcations.
Figure 5
. Single versus Dual Transmission Lines
14
IN
MPC9608
OUTPUT
BUFFER
R
S
= 36
Z
O
= 50
OutA
14
IN
MPC9608
OUTPUT
BUFFER
R
S
= 36
Z
O
= 50
OutB0
R
S
= 36
Z
O
= 50
OutB1
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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