参数资料
型号: MPC9608
厂商: Motorola, Inc.
英文描述: 1:10 LVCMOS Zero Delay Clock Buffer
中文描述: 1:10的LVCMOS零延迟时钟缓冲器
文件页数: 9/12页
文件大小: 423K
代理商: MPC9608
MPC9608
TIMING SOLUTIONS
9
Figure 9
. Output-to-output Skew t
SK(O)
The pin-to-pin skew is defined as the worst case difference in propa-
gation delay between any similar delay path within a single device.
V
CC
V
CC
÷
2
GND
V
CC
V
CC
÷
2
GND
t
SK(O)
V
CC
V
CC
÷
2
GND
V
CC
V
CC
÷
2
GND
t
(
)
CCLK
FB_IN
Figure 10
. Propagation delay (t
PD
, static phase offset)
test reference
The time from the PLL controlled edge to the non controlled edge, di-
vided by the time between PLL controlled edges, expressed as a per-
centage.
V
CC
V
CC
÷
2
GND
t
P
T
0
DC = t
P
/T
0
x
100%
Figure 11
. Output Duty Cycle (DC)
Figure 12. I/O Jitter
The deviation in t
0
for a controlled edge with respect to a t
0
mean in a
random sample of cycles.
T
JIT(
)
=
|
T
0
- T
1
mean
|
CCLK
FB_IN
Figure 13. Cycle-to-cycle Jitter
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs.
T
N
T
JIT(CC)
=
|
T
N
-T
N + 1
|
T
N + 1
Figure 14. Period Jitter
The deviation in cycle time of a signal with respect to the ideal period
over a random sample of cycles.
T
JIT(PER)
=
|
T
N
- 1
/
f
0
|
T
0
Figure 15. Output Transition Time Test Reference
t
F
t
R
V
CC
= 3.3 V
2.4
0.55
Figure 16. Setup and Hold Time (t
s
, t
H
) Test Reference
V
CC
V
CC
÷
2
GND
t
s
CCLK
CLK_STOP
V
CC
V
CC
÷
2
GND
t
H
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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