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| 型号： | MPC961CFAR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | PLASTIC, LQFP-32 |
| 文件页数： | 5/9页 |
| 文件大小： | 343K |
| 代理商： | MPC961CFAR2 |
5
MPC961C
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
481
Power Supply Filtering
The MPC961C is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily be
seen on a fully digital product. Analog circuitry is naturally sus-
ceptible to random noise, especially if this noise is seen on the
power supply pins. The MPC961C provides separate power
supplies for the output buffers (VCC) and the phase–locked
loop (VCCA) of the device. The purpose of this design tech-
nique is to isolate the high switching noise digital outputs from
the relatively sensitive internal analog phase–locked loop. In a
controlled environment such as an evaluation board this level
of isolation is sufficient. However, in a digital system environ-
ment where it is more difficult to minimize noise on the power
supplies a second level of isolation may be required. The sim-
plest form of isolation is a power supply filter on the VCCA pin
for the MPC961C.
Figure 3 illustrates a typical power supply filter scheme. The
MPC961C is most susceptible to noise with spectral content in
the 10kHz to 10MHz range. Therefore the filter should be de-
signed to target this range. The key parameter that needs to be
met in the final filter design is the DC voltage drop that will be
seen between the VCC supply and the VCCA pin of the
MPC961C. From the data sheet the ICCA current (the current
sourced through the VCCA pin) is typically 2mA (5mA maxi-
mum), assuming that a minimum of 2.375V (VCC = 3.3V or VCC
= 2.5V) must be maintained on the VCCA pin. The resistor RF
shown in Figure 3 must have a resistance of 270
(VCC =
3.3V) or 5 to 15
(VCC = 2.5V) to meet the voltage drop crite-
ria. The RC filter pictured will provide a broadband filter with
approximately 100:1 attenuation for noise whose spectral con-
tent is above 20kHz. As the noise frequency crosses the series
resonant point of an individual capacitor it’s overall impedance
begins to look inductive and thus increases with increasing
frequency. The parallel capacitor combination shown ensures
that a low impedance path to ground exists for frequencies well
above the bandwidth of the PLL.
Figure 3. Power Supply Filter
VCCA
VCC
MPC961C
10 nF
RF = 270 for VCC = 3.3V
RF = 5-15 for VCC = 2.5V
22 F
33...100 nF
RF
VCC
Although the MPC961C has several design features to mini-
mize the susceptibility to power supply noise (isolated power
and grounds and fully differential PLL) there still may be ap-
plications in which overall performance is being degraded due
to system power supply noise. The power supply filter
schemes discussed in this section should be adequate to elim-
inate power supply noise related problems in most designs.
Driving Transmission Lines
The MPC961C clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of less than 15
the drivers can drive
either parallel or series terminated transmission lines. For
more information on transmission lines the reader is referred to
application note AN1091.
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a point–to–
point scheme either series terminated or parallel terminated
transmission lines can be used. The parallel technique termi-
nates the signal at the end of the line with a 50
resistance to
VCC/2. This technique draws a fairly high level of DC current
and thus only a single terminated line can be driven by each
output of the MPC961C clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 4 illustrates
an output driving a single series terminated line vs two series
terminated lines in parallel. When taken to its extreme the fan-
out of the MPC961C clock driver is effectively doubled due to
its capability to drive multiple lines.
Figure 4. Single versus Dual Transmission Lines
14
IN
MPC961
OUTPUT
BUFFER
RS = 36
ZO = 50
OutA
14
IN
MPC961
OUTPUT
BUFFER
RS = 36
ZO = 50
OutB0
RS = 36
ZO = 50
OutB1
The waveform plots of Figure 5 show the simulation results
of an output driving a single line vs two lines. In both cases the
drive capability of the MPC961C output buffer is more than
sufficient to drive 50
transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta
of only 43ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used exclu-
sively to maintain the tight output–to–output skew of the
MPC961C. The output waveform in Figure 5 shows a step in
the waveform, this step is caused by the impedance mismatch
seen looking into the driver. The parallel combination of the
36
series resistor plus the output impedance does not match
the parallel combination of the line impedances. The voltage
wave launched down the two lines will equal:
VL = VS ( Zo / (Rs + Ro +Zo))
Zo = 50
|| 50
Rs = 36
|| 36
Ro = 14
VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)
= 1.31V
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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