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参数资料
| 型号： | MPC961PFA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | PLASTIC, LQFP-32 |
| 文件页数： | 4/9页 |
| 文件大小： | 162K |
| 代理商： | MPC961PFA |
MPC961P
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
495
Table 6. DC Characteristics (VCC = 2.5 V ± 5%, TA = –40° to 85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input HIGH Voltage
1.7
VCC + 0.3
V
LVCMOS
VIL
Input LOW Voltage
–0.3
0.7
V
LVCMOS
VPP
Peak-to-peak input voltage1
PECL_CLK, PECL_CLK
1.
Exceeding the specified VCMR/VPP window results in a tPD changes < 250 ps.
500
1000
mV
LVPECL
VCMR
Common Mode Rangea
PECL_CLK, PECL_CLK
1.2
VCC – 0.7
V
LVPECL
VOH
Output HIGH Voltage
1.8
V
IOH = –15 mA
2
2.
The MPC961P is capable of driving 50
transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission
line to a termination voltage of VTT. Alternatively, the device drives up two 50 series terminated transmission lines.
VOL
Output LOW Voltage
0.6
V
IOL = 15 mA
b
ZOUT
Output Impedance
18
26
IIN
Input Current
±120
A
CIN
Input Capacitance
4.0
pF
CPD
Power Dissipation Capacitance
8.0
10
pF
Per Output
ICCA
Maximum PLL Supply Current
2.0
5.0
mA
VCCA Pin
ICC
Maximum Quiescent Supply Current
mA
All VCC Pins
VTT
Output Termination Voltage
VCC ÷ 2
V
Table 7. AC Characteristics (VCC = 2.5 V ± 5%, TA = –40° to 85°C)
1
1.
AC characteristics apply for parallel output termination of 50
to V
TT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fREF
Input Frequency
F_RANGE = 0
F_RANGE = 1
100
50
200
100
MHz
fMAX
Maximum Output Frequency
F_RANGE = 0
F_RANGE = 1
100
50
200
100
MHz
fREFDC
Reference Input Duty Cycle
25
75
%
t()
Propagation Delay2
CCLK to FB_IN
(static phase offset)
2.
tPD applies for VCMR = VCC –1.3 V and VPP = 800 mV.
–50
175
ps
PLL locked
tsk(O)
Output-to-Output Skew3
3.
Refer to APPLICATIONS INFORMATION for part-to-part skew calculation.
90
150
ps
DCO
Output Duty Cycle
F_RANGE = 0
F_RANGE = 1
40
45
50
60
55
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.6 to 1.8 V
tPLZ,HZ
Output Disable Time
10
ns
tPZL,LZ
Output Enable Time
10
ns
tJIT(CC)
Cycle-to-Cycle Jitter
RMS (1
σ)4
4.
Refer to APPLICATIONS INFORMATION for calculation for other confidence factors than 1
σ.
15
ps
tJIT(PER)
Period Jitter
RMS (1
σ)
7.0
10
ps
tJIT()
I/O Phase Jitter
RMS (1
σ)F_RANGE = 0
F_RANGE = 1
0.0015
T
0.0010
T
ns
T = Clock Signal
Period
tlock
Maximum PLL Lock Time
10
ms
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