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参数资料
| 型号： | MPC9653AFA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9653 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, PLASTIC, LQFP-32 |
| 文件页数： | 6/12页 |
| 文件大小： | 344K |
| 代理商： | MPC9653AFA |
Advanced Clock Drivers Device Data
Freescale Semiconductor
3
MPC9653A
Table 1. Pin Configuration
Pin
I/O
Type
Function
PCLK, PCLK
Input
LVPECL
PECL reference clock signal
FB_IN
Input
LVCMOS
PLL feedback signal input, connect to QFB
VCO_SEL
Input
LVCMOS
Operating frequency range select
BYPASS
Input
LVCMOS
PLL and output divider bypass select
PLL_EN
Input
LVCMOS
PLL enable/disable
MR/OE
Input
LVCMOS
Output enable/disable (high-impedance tristate) and device reset
Q0–7
Output
LVCMOS
Clock outputs
QFB
Output
LVCMOS
Clock output for PLL feedback, connect to FB_IN
GND
Supply
Ground
Negative power supply (GND)
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply). It is recommended to use an external RC filter for
VCC
Supply
VCC
Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply
for correct operation
Table 2. Function Table
Control
Default
0
1
PLL_EN
1
Test mode with PLL bypassed. The reference clock (PCLK)
is substituted for the internal VCO output. MPC9653A is fully
static and no minimum frequency limit applies. All PLL
related AC characteristics are not applicable.
Selects the VCO output(1)
1. PLL operation requires BYPASS = 1 and PLL_EN = 1.
BYPASS
1
Test mode with PLL and output dividers bypassed. The
reference clock (PCLK) is directly routed to the outputs.
MPC9653A is fully static and no minimum frequency limit
applies. All PLL related AC characteristics are not
applicable.
Selects the output dividers.
VCO_SEL
1
VCO
÷ 1 (High frequency range). fREF =fQ0–7 =4 fVCO
VCO
÷ 2 (Low output range). fREF = fQ0–7 =8 fVCO
MR/OE
0
Outputs enabled (active)
Outputs disabled (high-impedance state) and reset of
the device. During reset the PLL feedback loop is open.
The VCO is tied to its lowest frequency. The length of the
reset pulse should be greater than one reference clock
cycle (PCLK).
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