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| 型号： | MPC9658ACR2 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9658 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, LEAD FREE, LQFP-32 |
| 文件页数： | 12/12页 |
| 文件大小： | 344K |
| 代理商： | MPC9658ACR2 |
Advanced Clock Drivers Device Data
Freescale Semiconductor
9
MPC9658
Figure 12. Output Duty Cycle (DC)
Figure 10. Output-to-Output Skew tSK(O)
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
VCC
VCC ÷ 2
GND
VCC
VCC ÷ 2
GND
tSK(O)
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
VCC
VCC ÷ 2
GND
tP
T0
DC = tP/T0 x 100%
Figure 14. Cycle-to-Cycle Jitter
Figure 13. I/O Jitter
Figure 16. Output Transition Time Test
Reference
tF
tR
VCC=3.3 V
2.4
0.55
TJIT() = |T0–T1mean|
PCLK
FB_IN
The deviation in t0 for a controlled edge with respect to a T0
mean in a random sample of cycles
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
TN
TJIT(CC) = |TN–TN+1|
TN+1
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles
TJIT(PER) = |TN–1/f0|
T0
Figure 15. Period Jitter
Figure 11. Propagation Delay (t(PD), static phase
offset) Test Reference
VCC
VCC ÷ 2
GND
t(PD)
PCLK
FB_IN
PCLK
VPP = 0.8V
VCMR =
VCC–1.3V
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