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参数资料
| 型号： | MPC97H74AE |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 1/13页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK GEN 1:14 3.3V 52-LQFP |
| 标准包装： | 160 |
| 类型： | PLL 时钟发生器 |
| PLL： | 带旁路 |
| 输入： | LVCMOS |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:14 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 125MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 52-LQFP |
| 供应商设备封装： | 52-TQFP（10x10） |
| 包装： | 托盘 |
DATASHEET
3.3 V 1:14 LVCMOS PLL Clock Generator
MPC97H74
NRND
MPC97H74 REVISION 5 JANUARY 9, 2013
1
2013 Integrated Device Technology, Inc.
The MPC97H74 is a 3.3 V compatible, 1:14 PLL based clock generator
targeted for high performance low-skew clock distribution in mid-range to
high-performance networking, computing and telecom applications. With output
frequencies up to 125 MHz and output skews less than 175 ps the device meets
the needs of the most demanding clock applications.
Features
1:14 PLL based low-voltage clock generator
3.3 V power supply
Internal power-on reset
Generates clock signals up to 125 MHz
Maximum output skew of 175 ps
Two LVCMOS PLL reference clock inputs
External PLL feedback supports zero-delay capability
Various feedback and output dividers (see application section)
Supports up to three individual generated output clock frequencies
Drives up to 28 clock lines
Ambient temperature range -40°C to +85°C
Pin and function compatible to the MPC974
52-lead Pb-free Package
NRND – Not Recommend for New Designs
Use replacement part ICS87974CYILF
The MPC97H74 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
MPC97H74 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path.
The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to
match the VCO frequency range.
The MPC97H74 features frequency programmability between the three output bank outputs as well as the output to input
relationships. Output frequency ratios of 1:1, 2:1, 3:1, 3:2, and 3:2:1 can be realized. Additionally, the device supports a separate
configurable feedback output which allows for a wide variety of input/output frequency multiplication alternatives. The VCO_SEL
pin provides an extended PLL input reference frequency range.
The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two
alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL
bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output
dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL
characteristics do not apply.
The MPC97H74 has an internal power-on reset.
The MPC97H74 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except XTAL) accept
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
transmission
lines. For series terminated transmission lines, each of the MPC97H74 outputs can drive one or two traces giving the devices an
effective fanout of 1:28. The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP package.
AE SUFFIX
52-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 848D-03
MPC97H74
3.3 V 1:14 LVCMOS
PLL CLOCK GENERATOR
NRND – Not Recommend for New Designs
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