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参数资料
| 型号： | MPC97H74AE |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 11/13页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK GEN 1:14 3.3V 52-LQFP |
| 标准包装： | 160 |
| 类型： | PLL 时钟发生器 |
| PLL： | 带旁路 |
| 输入： | LVCMOS |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:14 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 125MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 52-LQFP |
| 供应商设备封装： | 52-TQFP（10x10） |
| 包装： | 托盘 |
MPC97H74 REVISION 5 JANUARY 9, 2013
7
2013 Integrated Device Technology, Inc.
MPC97H74 Data Sheet
3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR
Using the MPC97H74 in Zero-Delay Applications
Nested clock trees are typical applications for the
MPC97H74. Designs using the MPC97H74 as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback of the
MPC97H74 clock driver allows for its use as a zero delay
buffer. The PLL aligns the feedback clock output edge with
the clock input reference edge resulting a near zero delay
through the device (the propagation delay through the device
is virtually eliminated). The maximum insertion delay of the
device in zero-delay applications is measured between the
reference clock input and any output. This effective delay
consists of the static phase offset, I/O jitter (phase or
long-term jitter), feedback path delay and the
output-to-output skew error relative to the feedback output.
Calculation of Part-to-Part Skew
The MPC97H74 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC97H74 are connected together, the maximum overall
timing uncertainty from the common CCLK input to any
output is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
Due to the statistical nature of I/O jitter a rms value (1
) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 11.
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device.
Due to the frequency dependence of the static phase
offset and I/O jitter, using Figure 6. MPC97H74 I/O Jitter and
Figure 7. MPC97H74 I/O Jitter to predict a maximum I/O jitter
and the specified t() parameter relative to the input reference
frequency results in a precise timing performance analysis.
In the following example calculation a I/O jitter confidence
factor of 99.7 percent (
3 ) is assumed, resulting in a worst
case timing uncertainty from the common input reference
clock to any output of –470 ps to +320 ps relative to CCLK
(PLL feedback =
8, reference frequency = 50 MHz, VCO
frequency = 400 MHz, I/O jitter = 15 ps rms max., static phase
offset t() = –250 ps to +100 ps):
tSK(PP) = [–250 ps...+100 ps] + [–175 ps...175 ps] +
[(15 ps
–3)...(15 ps 3)] + tPD, LINE(FB)
tSK(PP) = [–470 ps...+320 ps] + tPD, LINE(FB)
Figure 5. MPC97H74 Max. Device-to-Device Skew
tPD, LINE(FB)
tJIT()
tSK(O)
—t()
+t()
tJIT()
tSK(O)
tSK(PP)
Max. Skew
CCLKCommon
QFBDevice 1
Any QDevice 1
QFBDevice2
Any QDevice 2
Table 11. Confidence Factor CF
CF
Probability of Clock Edge Within The Distribution
1
0.68268948
2
0.95449988
3
0.99730007
4
0.99993663
5
0.99999943
6
0.99999999
Maximum I/O Phase Jitter (RMS) versus Frequency
Parameter: PLL Feedback Divider FB
200
250
300
350
400
450
500
100
80
60
40
20
0
FB =
32
FB =
16
FB =
8
VCO Frequency (MHz)
t jit
(
)[p
s]
RMS
Figure 6. MPC97H74 I/O Jitter
Figure 7. MPC97H74 I/O Jitter
Maximum I/O Phase Jitter (RMS) versus Frequency
Parameter: PLL Feedback Divider FB
160
140
120
100
80
60
40
20
0
200
250
300
350
400
450
500
VCO Frequency (MHz)
t jit
(
)[p
s]
R
M
S
FB
12
FB
48
FB
24
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