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参数资料
| 型号： | MPC97H74FA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 97H SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封装： | LQFP-52 |
| 文件页数： | 2/12页 |
| 文件大小： | 240K |
| 代理商： | MPC97H74FA |
Advanced Clock Driver Devices
10
Freescale Semiconductor
MPC97H74
Figure 13. Output-to-Output Skew tSK(O)
Figure 14. Propagation Delay (t(), Static Phase
Offset) Test Reference
Figure 15. Output Duty Cycle (DC)
The pin-to-pin skew is defined as the worst case difference in
propagation delay between any similar delay path within a
single device
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
VCC
VCC ÷ 2
GND
VCC
VCC ÷ 2
GND
tSK(O)
VCC
VCC ÷ 2
GND
tP
t0
DC = tP/t0 x 100%
VCC
VCC ÷ 2
GND
VCC
VCC ÷ 2
GND
t()
CCLKx
FB_IN
tJIT() = |t0 – t1mean|
CCLKx
FB_IN
The deviation in t0 for a controlled edge with respect to a t0
mean in a random sample of cycles
Figure 16. I/O Jitter
Figure 17. Cycle-to-Cycle Jitter
Figure 18. Period Jitter
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles
tN
tJIT(CC) = |tN – tN + 1|
tN+1
tJIT(PER) = |tN – (1 ÷ f0)|
t0
tF
tR
VCC = 3.3 V
2.4
0.55
Figure 19. Output Transition Time Test Reference
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