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参数资料
| 型号： | MPC9855VFR2 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PBGA100 |
| 封装： | 11 X 11 MM, 1 MM PITCH, MAPBGA-100 |
| 文件页数： | 6/12页 |
| 文件大小： | 260K |
| 代理商： | MPC9855VFR2 |
Advanced Clock Drivers Devices
Freescale Semiconductor
3
MPC9855
Table 1. Pin Configurations
Pin
I/O
Type
Function
Supply
Active/State
CLK
Input
LVCMOS PLL Reference Clock Input (pull-down)
VDD
PCLK, PCLK
Input
LVPECL
PLL reference clock input
(PCLK — pull-down, PCLK — pull-up and pull-down)
VDD
—
QA0, QA1,
QA2, QA3
Output
LVCMOS Clock Outputs
VDDOA
—
QB0, QB1,
QB2, QB3
Output
LVCMOS Clock Outputs
VDDOB
—
REF_OUT0
REF_OUT1
Output
LVCMOS Reference Output (25 MHz or 33 MHz)
VDD
—
XTAL_IN
Input
LVCMOS Crystal Oscillator Input Pin
VDD
—
XTAL_OUT
Output
LVCMOS Crystal Oscillator Output Pin
VDD
—
CLK_SEL
Input
LVCMOS Select between CLK and PCLK input (pull-down)
VDD
High
XTAL_SEL
Input
LVCMOS Select between External Input and Crystal Oscillator Input
(pull-down)
VDD
High
REF_33 MHz
Input
LVCMOS Selects 33MHz input (pull-down)
VDD
High
REF_OUT1_E
Input
LVCMOS Enables REF_OUT1 output (pull-down)
VDD
High
MR
Input
LVCMOS Master Reset (pull-up)
VDD
Low
PLL_BYPASS
Input
LVCMOS Select PLL or static test mode (pull-down)
VDD
High
CLK_A[0:5](1)
1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)
Input
LVCMOS Configures Bank A clock output frequency (pull-up)
VDD
—
CLK_B[0:5](2)
2. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)
Input
LVCMOS Configures Bank B clock output frequency (pull-up)
VDD
—
VDD
—
3.3 V Supply
—
VDDA
—
Analog Supply
—
VDDOA
—
Output Supply — Bank A
—
VDDOB
—
Output Supply — Bank B
—
GND
—
Ground
—
Table 2. Function Table
Control
Default
0
1
CLK_SEL
0
CLK
PCLK
XTAL_SEL
0
CLKx
XTAL
PLL_BYPASS
0
Normal
Bypass
REF_OUT1_E
0
Disables REF_OUT1
Enables REF_OUT1
REF_33 MHz
0
Selects 25 MHz Reference
Selects 33 MHz Reference
MR
1
Reset
Normal
CLK_A and CLK_B control output frequencies. See Table 3 for specific device configuration
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相关代理商/技术参数 |
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| MPC9855VM | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9855VMR2 | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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| MPC9865VMR2 | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9893 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Low Voltage PLL Intelligent Dynamic Clock (IDCS) Switch |
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