- 您现在的位置：买卖IC网 > PDF目录29137 > MPC993FA (INTEGRATED DEVICE TECHNOLOGY INC) 993 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 PDF资料下载
参数资料
| 型号： | MPC993FA |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 993 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | PLASTIC, LQFP-32 |
| 文件页数： | 4/6页 |
| 文件大小： | 298K |
| 代理商： | MPC993FA |
MPC993
MOTOROLA
TIMING SOLUTIONS
DL207 — Rev 0
4
Applications Information
The MPC993 is a dual clock PLL with on–chip Intelligent
Dynamic Clock Switch (IDCS) circuitry.
Definitions
primary clock: The input CLK selected by Sel_Clk.
secondary clock: The input CLK NOT selected by Sel_Clk.
PLL reference signal: The CLK selected as the PLL
reference signal by Sel_Clk or IDCS. (IDCS can override
Sel_Clk).
Status Functions
Clk_Selected: Clk_Selected (L) indicates CLK0 is selected
as the PLL reference signal. Clk_Selected (H) indicates
CLK1 is selected as the PLL reference signal.
INP_BAD: Latched (H) when it’s CLK is stuck (H) or (L) for at
least one Ext_FB period (Pos to Pos or Neg to Neg). Cleared
(L) on assertion of Alarm_Reset.
Control Functions
Sel_Clk: Sel_Clk (L) selects CLK0 as the primary clock.
Sel_Clk (H) selects CLK1 as the primary clock.
Alarm_Reset: Asserted by a negative edge. Generates a
one–shot reset pulse that clears INPUT_BAD latches and
Clk_Selected latch.
PLL_En: While (L), the PLL reference signal is substituted
for the VCO output.
MR: While (L), internal dividers are held in reset which holds
all Q outputs LOW.
Man Override (H)
(IDCS is disabled, PLL functions normally). PLL reference
signal (as indicated by Clk_Selected) will always be the CLK
selected by Sel_Clk. The status function INP_BAD is active
in Man Override (H) and (L).
Man Override (L)
(IDCS is enabled, PLL functions enhanced). The first CLK
to fail will latch it’s INP_BAD (H) status flag and select the
other input as the Clk_Selected for the PLL reference clock.
Once latched, the Clk_Selected and INP_BAD remain
latched until assertion of Alarm_Reset which clears all
latches (INP_BADs are cleared and Clk_Selected =
Sel_Clk). NOTE: If both CLKs are bad when Alarm_Reset is
asserted, both INP_BADs will be latched (H) after one
Ext_FB period and Clk_Selected will be latched (L) indicating
CLK0 is the PLL reference signal. While neither INP_BAD is
latched (H), the Clk_Selected can be freely changed with
Sel_Clk. Whenever a CLK switch occurs, (manually or by
IDCS), following the next negative edge of the newly selected
PLL reference signal, the next positive edge pair of Ext_FB
and the newly selected PLL reference signal will slew to
alignment.
To calculate the overall uncertainty between the input
CLKs and the outputs from multiple MPC993’s, the following
procedure should be used. Assuming that the input CLKs to
all MPC993’s are exactly in phase, the total uncertainty will
be the sum of the static phase offset, max I/O jitter, and
output to output skew.
During a dynamic switch, the output phase between two
devices may be increased for a short period of time. If the two
input CLKs are 400ps out of phase, a dynamic switch of an
MPC993 will result in an instantaneous phase change of
400ps to the PLL reference signal without a corresponding
change in the output phase (due to the limited response of
the PLL). As a result, the I/O phase of a device, undergoing
this switch, will initially be 400ps and diminish as the PLL
slews to its new phase alignment. This transient timing issue
should be considered when analyzing the overall skew
budget of a system.
Hot insertion and withdrawal
In PECL applications, a powered up driver will experience
a low impedance path through an MPC993 input to its
powered down VCC pins. In this case, a 100 ohm series
resistance should be used in front of the input pins to limit the
driver current. The resistor will have minimal impact on the
rise and fall times of the input signals.
Acquiring Frequency Lock
1. While the MPC993 is receiving a valid CLK signal, assert
Man_Override HIGH.
2. The PLL will phase and frequency lock within the specified
lock time.
3. Apply a HIGH to LOW transition to Alarm_Reset to reset
Input Bad flags.
4. De–assert Man_Override LOW to enable Intelligent
Dynamic Clock Switch mode.
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
MPC993
Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver
NETCOM
IDT Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC993
4
相关PDF资料 |
PDF描述 |
|---|---|
| MPC9952FAR2 | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9952FA | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9993ACR2 | 9993 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9993AC | 9993 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MSFLDL-TTL-200 | ACTIVE DELAY LINE, TRUE OUTPUT, SIP4 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9992 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:3.3 DIFFRERENTIAL ECL/PECL PLL CLOCK GENERATOR |
| MPC9992AC | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9992ACR2 | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9992FA | 功能描述:锁相环 - PLL 2.5 3.3V 400MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| MPC9992FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
发布紧急采购，3分钟左右您将得到回复。