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参数资料
| 型号： | MPF4856RLRM |
| 厂商： | ON SEMICONDUCTOR |
| 元件分类： | 小信号晶体管 |
| 英文描述： | 40 V, N-CHANNEL, Si, SMALL SIGNAL, JFET, TO-92 |
| 封装： | CASE 29-11, TO-226AA, 3 PIN |
| 文件页数： | 3/4页 |
| 文件大小： | 167K |
| 代理商： | MPF4856RLRM |
MPF4856
http://onsemi.com
783
Figure 5. Switching Time Test Circuit
10
2.0
20
3.0
5.0
7.0
0.5
1.0
3.0
30
5.0
0.3
0.1
10
0.05
0.03
VR, REVERSE VOLTAGE (VOLTS)
C,
CAP
ACIT
ANCE
(pF)
50
170
20
-10
-40
80
140
-70
r
1.8
1.0
2.0
1.2
1.4
1.6
0.8
0.6
0.4
,DRAIN-SOURCE
ON-ST
AT
E
ds(on)
RESIST
ANCE
(NORMALIZED)
Tchannel, CHANNEL TEMPERATURE (°C)
1.5
1.0
110
-VDD
VGG
RGG
RT
RGEN
50
VGEN
RK
RD
OUTPUT
INPUT
50
SET VDS(off) = 10 V
INPUT PULSE
tr ≤ 0.25 ns
tf ≤ 0.5 ns
PULSE WIDTH = 2.0 s
DUTY CYCLE ≤ 2.0%
RGG & RK
RD′ = RD(RT + 50)
RD + RT + 50
Figure 6. Typical Forward Transfer Admittance
NOTE 1
The switching characteristics shown above were measured using a
test circuit similar to Figure 5. At the beginning of the switching in-
terval, the gate voltage is at Gate Supply Voltage (–VGG). The
Drain–Source Voltage (VDS) is slightly lower than Drain Supply
Voltage (VDD) due to the voltage divider. Thus Reverse Transfer
Capacitance (Crss) or Gate–Drain Capacitance (Cgd) is charged to
VGG + VDS.
During the turn–on interval, Gate–Source Capacitance (Cgs) dis-
charges through the series combination of RGen and RK. Cgd must
discharge to VDS(on) through RG and RK in series with the parallel
combination of effective load impedance (R
′D) and Drain–Source
Resistance (rds). During the turn–off, this charge flow is reversed.
Predicting turn–on time is somewhat difficult as the channel re-
sistance rds is a function of the gate–source voltage. While Cgs dis-
charges, VGS approaches zero and rds decreases. Since Cgd dis-
charges through rds, turn–on time is non–linear. During turn–off, the
situation is reversed with rds increasing as Cgd charges.
The above switching curves show two impedance conditions:
1) RK is equal to RD′ which simulates the switching behavior of cas-
caded stages where the driving source impedance is normally the
load impedance of the previous stage, and 2) RK = 0 (low imped-
ance) the driving source impedance is that of the generator.
Figure 7. Typical Capacitance
ID, DRAIN CURRENT (mA)
2.0
5.0
3.0
7.0
0.5
1.0
3.0
7.0
5.0
50
30
10
20
0.7
2.0
10
20
,FOR
W
ARD
TRANSFER
ADMITT
ANCE
(mmhos)
fsy
80
120
160
200
1.0
3.0
5.0
2.0
VGS, GATE-SOURCE VOLTAGE (VOLTS)
4.0
0
40
6.0
7.0
8.0
0
r
,DRAIN-SOURCE
ON-ST
AT
E
ds(on)
RESIST
ANCE
(NORMALIZED)
Tchannel = 25°C
(Cds IS NEGLIGIBLE)
Cgs
Tchannel = 25°C
VDS = 15 V
Figure 8. Effect of Gate–Source Voltage
On Drain–Source Resistance
Figure 9. Effect of Temperature On
Drain–Source On–State Resistance
MPF4392
MPF4391
MPF4393
Cgd
ID = 1.0 mA
VGS = 0
IDSS
= 10
mA
25
mA
50 mA 75 mA 100 mA
125 mA
Tchannel = 25°C
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