参数资料
型号: MPSA55
厂商: MICRO COMMERCIAL COMPONENTS
元件分类: 小信号晶体管
英文描述: 50,000 SYSTEM GATE 1.8V FPGA - NOT RECOMMENDED for NEW DESIGN
中文描述: 500 mA, 60 V, PNP, Si, SMALL SIGNAL TRANSISTOR, TO-92
封装: PLASTIC PACKAGE-3
文件页数: 1/1页
文件大小: 340K
代理商: MPSA55
MPSA55
MPSA56
PNP Silicon
Amplifier Transistor
TO-92
DIMENSIONS
DIM
A
B
C
D
E
G
INCHES
MIN
.175
.175
.500
.016
.135
.095
MM
MAX
.185
.185
---
.020
.145
.105
MIN
4.45
4.46
12.7
0.41
3.43
2.42
MAX
4.70
4.70
---
0.63
3.68
2.67
NOTE
Features
Capable of 1.5Watts of Power Dissipation.
Collector-current 500mA
Collector-base Voltage 80V
Operating and storage junction temperature range: -55
O
C to +150
O
C
Maximum Ratings
Symbol
V
CEO
Collector-Emitter Voltage
V
CBO
Collector-Base Voltage
V
EBO
Emitter-Base Voltage
I
C
Collector Current Continuous
P
D
Total Device Dissipation @T
A
=25
O
C
Derate above 25
C
P
D
Total Device Dissipation @T
A
=25
O
C
Derate above 25
C
T
J
Junction Temperature
T
STG
Storage Temperature
Electrical Characteristics @ 25
O
C Unless Otherwise Specified
Symbol
Parameter
OFF CHARACTERISTICS
V
(BR)CEO
Collector-Emitter Breakdown Voltage
(1)
(I
C
=1.0mAdc, I
B
=0) MPSA55
MPSA56
V
(BR)EBO
Emitter-Base Breakdown Voltage
(I
E
=100uAdc, I
C
=0)
I
CES
Collector Cutoff Current
(V
CE
=60Vdc, I
B
=0)
I
CBO
Collector Cutoff Current
(V
CB
=60Vdc, I
E
=0) MPSA55
(V
CB
=80Vdc, I
E
=0) MPSA56
ONCHARACTERISTICS
(1)
h
FE(1)
DC Current Gain
(I
C
=10mAdc, V
CE
=1.0Vdc)
h
FE(2)
DC Current Gain
(I
C
=100mAdc, V
CE
=1.0Vdc)
V
CE(sat)
Collector-Emitter Saturation Voltage
(I
C
=100mAdc, I
B
=10mAdc)
V
BE(on)
Base-Emitter Saturation Voltage
(I
C
=100mAdc, V
CE
=1.0Vdc)
SMALL-SIGNAL CHARACTERISTICS
f
T
Current-Gain – Bandwidth Product
(3)
(I
C
=100mAdc, V
CE
=1.0Vdc,
f=100MHz) MPSA55
MPSA56
1.
Pulse Test: Pulse Width<300us, Duty Cycle<2.0%
2.
f
T
is defined as the frequency at which |h
fe
| extrapolates to unity.
Rating
Rating
80
80
4.0
500
625
5.0
1.5
12
-55 to +150
-55 to +150
Unit
V
V
V
mA
mW
mW/
O
C
W
mW/
O
C
O
C
O
C
Min
Max
Units
60
80
4.0
Vdc
Vdc
0.1
uAdc
0.1
0.1
uAdc
100
100
0.25
1.2
Vdc
Vdc
50
MHz
A
E
B
C
D
G
Pin Configuration
Bottom View
C
B
E
omp
onents
21201 Itasca Street Chatsworth
!
"#
"#
$ %
!
M C C
www.
mc c semi
.c om
相关PDF资料
PDF描述
MPSA56 50,000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
MPSA55 50,000 SYSTEM GATE 1.8V FPGA - NOT RECOMMENDED for NEW DESIGN
MPSA56 Mini size of Discrete semiconductor elements
MPSA55 Amplifier Transistors
MPSA56 50,000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
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