
Memory Interface
ARM DDI 0165B
Copyright 2000 ARM Limited. All rights reserved.
4-7
4.5
Endian effects for instruction fetches
The ARM9E-S performs 32-bit or 16-bit instruction fetches depending on whether the
processor is in ARM or Thumb state. The processor state can be determined externally
by the value of the ITBIT signal. When this signal is LOW, the processor is in ARM
state, and 32-bit instructions are fetched. When ITBIT is HIGH, the processor is in
Thumb state and 16-bit instructions are fetched.
The address produced by the ARM9E-S is always halfword-aligned. However, the
memory system must ignore bit 1of the address, depending on the size of the instruction
request. The significant address bits are listed in
Table 4-3.When a halfword instruction fetch is performed, a 32-bit memory system can return the
complete 32-bit word, and the ARM9E-S extracts the valid halfword field from it. The
field extracted depends on the state of the CFGBIGEND signal, which determines the
The fields extracted by the ARM9E-S are shown in
Table 4-4.When connecting 8-bit or 16-bit memory systems to the ARM9E-S, ensure that the data
is presented to the correct byte lanes on the ARM9E-S as shown in
Table 4-5.Table 4-3 Significant address bits
ITBIT
Width
Significant
address bits
1
Halfword
IA[31:1]
0Word
IA[31:2]
Table 4-4 32-bit instruction fetches
ITBIT
IA[1]
Little-endian
CFGBIGEND = 0
Big-endian
CFGBIGEND = 1
0
X
INSTR[31:0]
Table 4-5 Halfword accesses
ITBIT
IA[1]
Little-endian
CFGBIGEND = 0
Big-endian
CFGBIGEND = 1
1
0
INSTR[15:0]
INSTR[31:16]
1
INSTR[31:16]
INSTR[15:0]