
Debug Interface and EmbeddedICE-RT
7-18
Copyright 2000 ARM Limited. All rights reserved.
ARM DDI 0165B
You can use the following instructions to access these registers:
MRC p14, 0, Rd, c0, c0
This returns the debug comms control register into Rd.
MCR p14, 0, Rn, c1, c0
This writes the value in Rn to the comms data write register.
MRC p14, 0, Rd, c1, c0
This returns the debug data read register into Rd.
Note
The Thumb instruction set does not support coprocessor instructions. Therefore, the
processor must be in ARM state before you can access the debug comms channel.
7.8.3
Comms channel monitor mode debug status register
The coprocessor 14 monitor mode debug status register is provided for use by a debug
monitor when the ARM9E-S is configured into the monitor mode debug mode.
The coprocessor 14 monitor mode debug status register is a 1-bit wide read/write
Figure 7-9 Coprocessor 14 monitor mode debug status register format
Bit 0 of the register, the DbgAbt bit, indicates whether the processor took a Prefetch or
Data Abort in the past because of a breakpoint or watchpoint. If the ARM9E-S core
takes a Prefetch Abort as a result of a breakpoint or watchpoint, then the bit is set. If on
a particular instruction or data fetch, both the debug abort and external abort signals are
asserted, the external abort takes priority and the DbgAbt bit is not set. You can read or
write the DbgAbt bit using MRC or MCR instructions.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
00 00 00000000000000000000000000 0
DbgAbt bit