![](http://datasheet.mmic.net.cn/20000/MQ80C52CXXX-36SBR_datasheet_1389801/MQ80C52CXXX-36SBR_854.png)
854
6437E–ATARM–23-Apr-13
SAM9M11
38.6.8
Interrupt Status Register
Name:
EMAC_ISR
Address:
0xFFFBC024
Access:
Read-write
MFD: Management Frame Done
The PHY maintenance register has completed its operation. Cleared on read.
RCOMP: Receive Complete
A frame has been stored in memory. Cleared on read.
RXUBR: Receive Used Bit Read
Set when a receive buffer descriptor is read with its used bit set. Cleared on read.
TXUBR: Transmit Used Bit Read
Set when a transmit buffer descriptor is read with its used bit set. Cleared on read.
TUND: Ethernet Transmit Buffer Underrun
The transmit DMA did not fetch frame data in time for it to be transmitted or hresp returned not OK. Also set if a used bit
is read mid-frame or when a new transmit queue pointer is written. Cleared on read.
RLE: Retry Limit Exceeded
Cleared on read.
TXERR: Transmit Error
Transmit buffers exhausted in mid-frame - transmit error. Cleared on read.
TCOMP: Transmit Complete
Set when a frame has been transmitted. Cleared on read.
ROVR: Receive Overrun
Set when the receive overrun status bit gets set. Cleared on read.
HRESP: Hresp not OK
Set when the DMA block sees a bus error. Cleared on read.
PFR: Pause Frame Received
Indicates a valid pause has been received. Cleared on a read.
PTZ: Pause Time Zero
Set when the pause time register, 0x38 decrements to zero. Cleared on a read.WOL: Wake On LAN
Set when a WOL event has been triggered (This flag can be set even if the EMAC is not clocked). Cleared on a read.
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–
WOL
PTZ
PFR
HRESP
ROVR
–
76543210
TCOMP
TXERR
RLE
TUND
TXUBR
RXUBR
RCOMP
MFD