参数资料
型号: MR256A08BYS35
厂商: Everspin Technologies Inc
文件页数: 14/24页
文件大小: 0K
描述: IC MRAM 256KB 35NS 44TSOP
标准包装: 135
格式 - 存储器: RAM
存储器类型: MRAM(磁阻 RAM)
存储容量: 256K (32K x 8)
速度: 35ns
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 44-TSOP(0.400",10.16mm 宽)
供应商设备封装: 44-TSOP II
包装: 托盘
其它名称: 819-1024
MR256A08B
Write Mode
Table 10 – Write Cycle Timing 1 (W Controlled)
Parameter 1
Write cycle time 2
Address set-up time
Address valid to end of write (G high)
Address valid to end of write (G low)
Write pulse width (G high)
Write pulse width (G low)
Data valid to end of write
Data hold time
Write low to data Hi-Z 3
Write high to output active 3
Write recovery time
Symbol
tAVAV
tAVWL
tAVWH
tAVWH
tWLWH
tWLEH
tWLWH
tWLEH
tDVWH
tWHDX
tWLQZ
tWHQX
tWHAX
Min
35
0
18
20
15
15
10
0
0
3
12
Max
-
-
-
-
-
-
-
-
12
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1.
2.
3.
All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or
after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must re-
main in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being
asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
All write cycle timings are referenced from the last valid address to the first transition address.
This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage. At any
given voltage or temperature, t (max) < t (min)
WLQZ WHQX
Copyright ? 2013 Everspin Technologies
14
MR256A08B Rev. 6, 10/2013
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