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参数资料
| 型号： | MR2A08AYS35R |
| 厂商： | Everspin Technologies Inc |
| 文件页数： | 10/14页 |
| 文件大小： | 0K |
| 描述： | IC MRAM 4MBIT 35NS 44TSOP |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | MRAM（磁阻 RAM） |
| 存储容量： | 4M (512K x 8) |
| 速度： | 35ns |
| 接口： | 并联 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 44-TSOP（0.400"，10.16mm 宽） |
| 供应商设备封装： | 44-TSOP II |
| 包装： | 带卷 (TR) |
Timing Specifications
Table 3.5 Write Cycle Timing 2 (E Controlled) 1
MR2A08A
Parameter
Write cycle time 2
Address set-up time
Address valid to end of write ( G high)
Address valid to end of write ( G low)
Enable to end of write ( G high)
Enable to end of write ( G low) 3
Data valid to end of write
Data hold time
Write recovery time
Symbol
t AVAV
t AVEL
t AVEH
t AVEH
t ELEH
t ELWH
t ELEH
t ELWH
t DVEH
t EHDX
t EHAX
Min
35
0
18
20
15
15
10
0
12
Max
-
-
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in
steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted
low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
All write cycle timings are referenced from the last valid address to the first transition address.
2
3
If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the
same time or before W goes high, the output will remain in a high-impedance state.
Figure 3.5 Write Cycle Timing 2 (E Controlled)
t AVAV
A (ADDRESS)
E (CHIP ENABLE)
t AVEL
t AVEH
t ELEH
t ELWH
t EHAX
W (WRITE ENABLE)
t DVEH
t EHDX
D (DATA IN)
Q (DATA OUT)
Hi-Z
Data Valid
Everspin Technologies ? 2012
10
MR2A08A Rev. 6, 8/2012
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