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参数资料
型号： MSC1214Y2PAGR
厂商： TEXAS INSTRUMENTS INC
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64
封装： GREEN, PLASTIC, TQFP-64
文件页数： 101/111页
文件大小： 1102K
代理商： MSC1214Y2PAGR
MSC1211, MSC1212
MSC1213,MSC1214
SBAS323G JUNE 2004 REVISED OCTOBER 2007
www.ti.com
9
AC ELECTRICAL CHARACTERISTICS(1)(2): DVDD = 2.7V to 5.25V
2.7V to 3.6V
4.75V to 5.25V
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNITS
System Clock
fOSC(3)
4
External Crystal Frequency (fOSC)
1
24
1
33
MHz
1/tOSC(3)
4
External Clock Frequency (fOSC) at +85°C
0
24
0
40
MHz
1/tOSC(3)
4
External Clock Frequency (fOSC) at +125°C
0
22
0
36
MHz
fOSC(3)
4
External Ceramic Resonator Frequency (fOSC)
1
12
1
12
MHz
Program Memory
tLHLL
1
ALE Pulse Width
1.5tCLK 5
ns
tAVLL
1
Address Valid to ALE Low
0.5tCLK 10
0.5tCLK 7
ns
tLLAX
1
Address Hold After ALE Low
0.5tCLK
ns
tLLIV
1
ALE Low to Valid Instruction In
2.5tCLK 35
2.5tCLK 25
ns
tLLPL
1
ALE Low to PSEN Low
0.5tCLK
ns
tPLPH
1
PSEN Pulse Width
2tCLK 5
ns
tPLIV
1
PSEN Low to Valid Instruction In
2tCLK 40
2tCLK 30
ns
tPXIX
1
Input Instruction Hold After PSEN
5
ns
tPXIZ
1
Input Instruction Float After PSEN
tCLK 5
tCLK
ns
tAVIV
1
Address to Valid Instruction In
3tCLK 40
3tCLK 25
ns
tPLAZ
1
PSEN Low to Address Float
0
ns
Data Memory
tRLRH
2
RD Pulse Width (tMCS = 0)(4)
2tCLK 5
2tCLK 5
ns
tRLRH
2
RD Pulse Width (tMCS > 0)(4)
tMCS 5
ns
tWLWH
3
WR Pulse Width (tMCS = 0)(4)
2tCLK 5
ns
tWLWH
3
WR Pulse Width (tMCS > 0)(4)
tMCS 5
ns
tRLDV
2
RD Low to Valid Data In (tMCS = 0)(4)
2tCLK 40
2tCLK 30
ns
tRLDV
2
RD Low to Valid Data In (tMCS > 0)(4)
tMCS 40
tMCS 30
ns
tRHDX
2
Data Hold After Read
5
ns
tRHDZ
2
Data Float After Read (tMCS = 0)(4)
tCLK
ns
tRHDZ
2
Data Float After Read (tMCS > 0)(4)
2tCLK
ns
tLLDV
2
ALE Low to Valid Data In (tMCS = 0)(4)
2.5tCLK 40
2.5tCLK 25
ns
tLLDV
2
ALE Low to Valid Data In (tMCS > 0)(4)
tCLK + tMCS 40
tCLK + tMCS 25
ns
tAVDV
2
Address to Valid Data In (tMCS = 0)(4)
3tCLK 40
3tCLK 25
ns
tAVDV
2
Address to Valid Data In (tMCS > 0)(4)
1.5tCLK +tMCS 40
1.5tCLK +tMCS 25
ns
tLLWL
2, 3
ALE Low to RD or WR Low (tMCS = 0)(4)
0.5tCLK 5
0.5tCLK + 5
0.5tCLK 5
0.5tCLK + 5
ns
tLLWL
2, 3
ALE Low to RD or WR Low (tMCS > 0)(4)
tCLK 5
tCLK + 5
tCLK 5
tCLK + 5
ns
tAVWL
2, 3
Address to RD or WR Low (tMCS = 0)(4)
tCLK 5
ns
tAVWL
2, 3
Address to RD or WR Low (tMCS > 0)(4)
2tCLK 5
ns
tQVWX
3
Data Valid to WR Transition
8
5
ns
tWHQX
3
Data Hold After WR
tCLK 8
tCLK 5
ns
tRLAZ
2
RD Low to Address Float
0.5tCLK 5
ns
tWHLH
2, 3
RD or WR High to ALE High (tMCS = 0)(4)
5
ns
tWHLH
2, 3
RD or WR High to ALE High (tMCS > 0)(4)
tCLK 5
tCLK + 5
tCLK 5
tCLK + 5
ns
External Clock
tHIGH
4
High Time(5)
15
10
ns
tLOW
4
Low Time(5)
15
10
ns
tR
4
Rise Time(5)
5
ns
tF
4
Fall Time(5)
5
ns
(1) Parameters are valid over operating temperature range, unless otherwise specified.
(2) Load capacitance for Port 0, ALE, and PSEN = 100pF; load capacitance for all other outputs = 80pF.
(3) tCLK = 1/fOSC = one oscillator clock period for clock divider = 1.
(4) tMCS is a time period related to the Stretch MOVX selection. The following table shows the value of tMCS for each stretch selection:
(5) These values are characterized, but not 100% production tested.
MD2
MD1
MD0
MOVX DURATION
tMCS
0
2 Machine Cycles
0
1
3 Machine Cycles (default)
4tCLK
0
1
0
4 Machine Cycles
8tCLK
0
1
5 Machine Cycles
12tCLK
1
0
6 Machine Cycles
16tCLK
1
0
1
7 Machine Cycles
20tCLK
1
0
8 Machine Cycles
24tCLK
1
9 Machine Cycles
28tCLK
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