参数资料
型号: MSC1214Y2PAGR
厂商: TEXAS INSTRUMENTS INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64
封装: GREEN, PLASTIC, TQFP-64
文件页数: 98/111页
文件大小: 1102K
代理商: MSC1214Y2PAGR
MSC1211, MSC1212
MSC1213,MSC1214
SBAS323G JUNE 2004 REVISED OCTOBER 2007
www.ti.com
87
Timer 2 Capture MSB (RCAP2H)
7
6
5
4
3
2
1
0
Reset Value
SFR CBh
00h
RCAP2H
Timer 2 Capture MSB. This register is used to capture the TH2 value when Timer 2 is configured in capture mode.
bits 70
RCAP2H is also used as the MSB of a 16-bit reload value when Timer 2 is configured in auto-reload mode.
Timer 2 LSB (TL2)
7
6
5
4
3
2
1
0
Reset Value
SFR CCh
00h
TL2
Timer 2 LSB. This register contains the least significant byte of Timer 2.
bits 70
Timer 2 MSB (TH2)
7
6
5
4
3
2
1
0
Reset Value
SFR CDh
00h
TH2
Timer 2 MSB. This register contains the most significant byte of Timer 2.
bits 70
Program Status Word (PSW)
7
6
5
4
3
2
1
0
Reset Value
SFR D0h
CY
AC
F0
RS1
RS0
OV
F1
P
00h
CY
Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (during addition) or a borrow (during
bit 7
subtraction). Otherwise, it is cleared to ‘0’ by all arithmetic operations.
AC
Auxiliary Carry Flag. This bit is set to ‘1’ if the last arithmetic operation resulted in a carry into (during addition), or
bit 6
a borrow (during subtraction) from the high order nibble. Otherwise, it is cleared to ‘0’ by all arithmetic operations.
F0
User Flag 0. This is a bit-addressable, general-purpose flag for software control.
bit 5
RS1, RS0
Register Bank Select 10. These bits select which register bank is addressed during register accesses.
bits 43
RS1
RS0
REGISTER BANK
ADDRESS
0
00h 07h
0
1
08h 0Fh
1
0
2
10h 17h
1
3
18h 1Fh
OV
Overflow Flag. This bit is set to ‘1’ if the last arithmetic operation resulted in a carry (addition), borrow (subtraction),
bit 2
or overflow (multiply or divide). Otherwise, it is cleared to ‘0’ by all arithmetic operations.
F1
User Flag 1. This is a bit-addressable, general-purpose flag for software control.
bit 1
P
Parity Flag. This bit is set to ‘1’ if the modulo-2 sum of the 8 bits of the accumulator is 1 (odd parity), and cleared to
bit 0
‘0’ on even parity.
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