参数资料
型号: MSC1214Y2PAGTG4
厂商: TEXAS INSTRUMENTS INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64
封装: GREEN, PLASTIC, TQFP-64
文件页数: 3/111页
文件大小: 1102K
代理商: MSC1214Y2PAGTG4
MSC1211, MSC1212
MSC1213,MSC1214
SBAS323G JUNE 2004 REVISED OCTOBER 2007
www.ti.com
100
Seconds Timer Interrupt (SECINT)
7
6
5
4
3
2
1
0
Reset Value
SFR F9h
WRT
SECINT6
SECINT5
SECINT4
SECINT3
SECINT2
SECINT1
SECINT0
7Fh
This system clock is divided by the value of the 16-bit register MSECH:MSECL. Then, that 1ms timer tick is divided by the
register HMSEC which provides the 100ms signal used by this seconds timer. Therefore, this seconds timer can generate
an interrupt which occurs from 100ms to 12.8 seconds. Reading this register will clear the Seconds Interrupt; however, AI
in EICON (SFR D8h) must also be cleared. This Interrupt can be monitored in the AIE or AIPOL registers.
WRT
Write Control. Determines whether to write the value immediately or wait until the current count is finished.
bit 7
Read = 0.
0 = Delay Write Operation. The SEC value is loaded when the current count expires.
1 = Write Immediately. The counter is loaded once the CPU completes the write operation.
SECINT60 Seconds Count. Normal operation would use 100ms as the clock interval.
bits 60
Seconds Interrupt = (1 + SEC)
(HMSEC + 1) (MSEC + 1) tCLK.
Milliseconds Timer Interrupt (MSINT)
7
6
5
4
3
2
1
0
Reset Value
SFR FAh
WRT
MSINT6
MSINT5
MSINT4
MSINT3
MSINT2
MSINT1
MSINT0
7Fh
The clock used for this timer is the 1ms clock, which results from dividing the system clock by the values in registers
MSECH:MSECL. Reading this register is necessary for clearing the interrupt; however, AI in EICON (SFR D8h) must also
be cleared.
WRT
Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0.
bit 7
0 = Delay Write Operation. The MSINT value is loaded when the current count expires.
1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation.
MSINT60
Milliseconds Count. Normal operation would use 1ms as the clock interval.
bits 60
MS Interrupt Interval = (1 + MSINT)
(MSEC + 1) tCLK
One Microsecond Timer (USEC)
7
6
5
4
3
2
1
0
Reset Value
SFR FBh
0
FREQ5
FREQ4
FREQ3
FREQ2
FREQ1
FREQ0
03h
FREQ50
Clock Frequency 1. This value + 1 divides the system clock to create a 1
s Clock.
bits 50
USEC = CLK/(FREQ + 1). This clock is used to set Flash write time. See FTCON (SFR EFh).
One Millisecond Timer Low Byte (MSECL)
7
6
5
4
3
2
1
0
Reset Value
SFR FCh
MSECL7
MSECL6
MSECL5
MSECL4
MSECL3
MSECL2
MSECL1
MSECL0
9Fh
MSECL70 One Millisecond Timer Low Byte. This value in combination with the next register is used to create a 1ms clock.
bits 70
1ms = (MSECH
256 + MSECL + 1) tCLK. This clock is used to set Flash erase time. See FTCON (SFR EFh).
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